Semiconductor and optoelectronic devices

• US 9,419,031 B1
• Filed: 08/18/2014
• Issued: 08/16/2016
• Est. Priority Date: 10/07/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak
• Primary Examiner(s): Fourson, III, George
• Application Number:
  US14/461,539
• Time in Patent Office: 729 Days
• Field of Search: 257/432, 257/435, 257/440
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14605 Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/34 containing only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

An integrated device, including: a first mono-crystal layer including a plurality of image sensor pixels and alignment marks; an overlaying oxide on top of the first mono-crystal layer; and a second mono-crystal layer overlaying the oxide, where the second mono-crystal layer includes a plurality of single crystal transistors aligned to the alignment marks.

Claims

1. An integrated device, comprising:

an image sensor array and an image circuit array;

wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,

wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is thin isolation layer, and

wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and

wherein said second mono-crystal layer comprises a plurality of single crystal transistors,

wherein said image sensor array comprises a plurality of image sensor pixels,

wherein said image sensor pixels and said single crystal transistors are aligned to each other.

2. An integrated device according to claim 1,

wherein said second mono-crystal layer is less than 2 microns thick.

3. An integrated device according to claim 1,

wherein said first mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and

wherein said first image sensor layer is sensitive to a different spectrum than said second image sensor layer.

18. An integrated device according to claim 1,

wherein said single crystal transistors form a plurality of pixel control circuits.

4. An integrated device, comprising:

an image sensor array and an image circuit array;

wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,

wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is thin isolation layer, and

wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and

wherein said second mono-crystal layer comprises a plurality of single crystal transistors,

wherein said second mono-crystal layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first transistors layer and a second transistors layer.

5. An integrated device according to claim 4,

wherein said first mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and

wherein at least one of said two crystalline layers is less than 2 microns thick.

6. An integrated device according to claim 4,

wherein said single crystal transistors form a plurality of pixel control circuits.

19. An integrated device according to claim 4,

wherein said first mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and

wherein said first image sensor layer is sensitive to a different spectrum than said second image sensor layer.

7. An integrated device, comprising:

an image sensor array and an image circuit array;

wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,

wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is a thin isolation layer,

wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and

wherein through said thin isolation layer are a multiplicity of conducting vias, and

wherein said conducting vias have a diameter of less than 200 nm, and

a third mono-crystallized silicon layer underlying said second mono-crystallized silicon layer,

wherein said third mono-crystallized silicon layer comprises pixel electronics read-out and control circuits.

8. An integrated device according to claim 7,

wherein said image sensor array is bonded on top of said image circuit array forming two substantially parallel planes, and

wherein said bonded leaves a re-useable base wafer used to hold said mono-crystallized silicon layer.

9. An integrated device according to claim 7,

wherein said image sensor array comprises a first image sensor array and a second image sensor array, and

wherein said first image sensor array optical sensitivity is substantially different than said second image sensor array.

10. An integrated device according to claim 7,

wherein said second mono-crystalline silicon layer comprises a plurality of single crystal transistors, and

wherein said single crystal transistors form a plurality of pixel control circuits.

11. An integrated device according to claim 7,

wherein said second mono-crystallized silicon layer comprises an infra-red photo detector.

20. An integrated device according to claim 7,

wherein said first mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and

wherein said first image sensor layer is sensitive to a different spectrum than said second image sensor layer.

12. An integrated device, comprising:

an image sensor array and an image circuit array;

wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,

wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is thin isolation layer, and

wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and

a third mono-crystallized silicon layer underlying said first mono-crystallized silicon layer,

wherein said third mono-crystallized silicon layer comprises pixel electronics read-out and control circuits.

13. An integrated device according to claim 12,

wherein said image sensor array is bonded on top of said image circuit array forming two substantially parallel planes, and

wherein said bonded leaves a re-useable base wafer used to hold said mono-crystallized silicon layer.

14. An integrated device according to claim 12,

wherein said image sensor array comprises a first image sensor array and a second image sensor array, and

wherein said first image sensor array optical sensitivity is substantially different than said second image sensor array.

15. An integrated device according to claim 12, further comprising:

a multiplicity of through silicon layer conducting vias,

wherein said conducting vias have a diameter of less than 200 nm.

16. An integrated device according to claim 12,

wherein said second mono-crystallized silicon layer comprises an infra-red photo detector.

17. An integrated device according to claim 12,

wherein said image sensor array comprises a first image sensor array and a second image sensor array, and

wherein disposed between said first image sensor array and said second image sensor array is a wire grid polarizer.