Method of manufacturing a semiconductor component and structure

• US 9,419,069 B2
• Filed: 06/27/2014
• Issued: 08/16/2016
• Est. Priority Date: 10/01/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Holland, Phillip, Liu, Rong, Sharma, Umesh, Marreiro, David D, Liou, Der Min, Shastri, Sudhama C
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US14/317,739
• Publication Number:
  US 20140308795A1
• Time in Patent Office: 781 Days
• Field of Search: 257/528, 257/532, 438/329, 438/381
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having a major surface;

forming a first metallization system over the semiconductor material, the first metallization system comprising a first electrical contact to a first portion of the semiconductor material and a second electrical contact to a second portion of the semiconductor material;

forming a first dielectric structure over the first metallization system;

forming a first template over the first dielectric structure, the first template having openings that expose portions of the first dielectric structure;

forming a second metallization system on the exposed portions of the first dielectric structure, the second metallization system comprising a first electrically conductive structure on a first portion of the first dielectric structure and a second electrically conductive structure on a second portion of the first dielectric structure, the first electrically conductive structure having a central region, a first end, and second end and the second electrically conductive structure having a central region, a first end, and a second end, the first metallization system formed so that the first electrically conductive structure is laterally adjacent to and electrically isolated from the second electrically conductive structure;

forming a second dielectric structure over the second metallization system;

forming a second template over the second dielectric structure, the second template having openings that expose portions of the second dielectric structure; and

forming a third metallization system on the exposed portions of the second dielectric structure, the third metallization system comprising a third electrically conductive structure on a first portion of the second dielectric structure and a fourth electrically conductive structure on a fourth portion of the second dielectric structure, the third electrically conductive structure having a central region, a first end, and second end and the fourth electrically conductive structure having a central region, a first end, and a second end, the third metallization system formed so that the third electrically conductive structure is laterally adjacent to and electrically isolated from the fourth electrically conductive structure, and a portion of the central region of the third electrically conductive structure is laterally between a portion of the central region of the first electrically conductive structure and a portion of the central region of the second electrically conductive structure, and the portion of the central region of the second electrically conductive structure laterally is between the portion of the central region of the third electrically conductive structure and a portion of the central region of the fourth electrically conductive structure.

2. The method of claim 1, wherein forming the first template comprises forming a first photoresist structure over the first dielectric structure, the first photoresist structure having openings that expose the portions of the first dielectric structure.

3. The method of claim 2, wherein forming the second metallization system includes forming a first seed layer on the exposed portions of the first dielectric structure and electroplating a first electrically conductive material on the first seed layer.

4. The method of claim 3, wherein forming the second template comprises forming a second photoresist structure over the second dielectric structure, the second photoresist structure having openings that expose the portions of the second dielectric structure.

5. The method of claim 4, wherein forming the third metallization system includes forming a second seed layer on the exposed portions of the second dielectric structure and electroplating a second electrically conductive material on the second seed layer.

6. The method of claim 1, wherein forming the first dielectric structure includes forming a first layer of polyimide and forming the second dielectric structure includes forming a second layer of polyimide.