Integrated circuit comprising at least an integrated antenna

• US 9,419,071 B2
• Filed: 10/29/2015
• Issued: 08/16/2016
• Est. Priority Date: 07/28/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto, Finocchiaro, Alessandro
• Primary Examiner(s): Roman, Angel
• Application Number:
  US14/926,269
• Publication Number:
  US 20160049459A1
• Time in Patent Office: 292 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 29/0642 : Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An integrated circuit on a substrate including at least one peripheral portion that surrounds an active area and is realized close to at least one scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in its peripheral portion on different planes starting from the substrate and realizes an integrated antenna for the circuit.

Claims

1. An integrated circuit, comprising:

a substrate including a peripheral portion that surrounds an active circuit area, wherein said peripheral portion is adjacent a scribe line;

a seal ring structure formed by a plurality of pillar structures distributed in the peripheral portion in an arrangement extending parallel to the scribe line, each pillar structure formed by a plurality of first conductive lines arranged in different planes and interconnected by vertical conductive connections; and

a first antenna structure formed by a first antenna line arranged in said different planes, said first antenna line including a first line portion positioned between the pillar structures of the seal ring structure and the scribe line and a second line portion positioned between the pillar structures of the seal ring structure and the active circuit area.

2. The integrated circuit of claim 1, wherein said first first antenna line of the first antenna structure further comprises a third line portion electrically interconnecting the first line portion to the second line portion, said third line portion positioned between adjacent ones of the pillar structures.

3. The integrated circuit of claim 2, wherein said first, second and third line portions form a serpentine line.

4. The integrated circuit of claim 1, wherein said first line portion of the first antenna line of the first antenna structure is positioned on an opposite side each pillar structure from said second line portion.

5. The integrated circuit of claim 4, wherein said first antenna line of the first antenna structure further comprises a plurality of third line portions, each third line portion electrically interconnecting the first line portion to the second line portion, and each third line portion positioned to extend between adjacent ones of the pillar structures.

6. The integrated circuit of claim 1, wherein said vertical conductive connections include a bottom-most set of vertical conductive connections between a bottom-most one of the first conductive lines and a well formed in the substrate, wherein the well is oppositely doped relative to the substrate so as to provide an integrated diode.

7. The integrated circuit of claim 1, further comprising a plurality of spaced apart doped regions in the substrate, said doped regions extending perpendicular to the scribe line and extending from a first end located in active circuit area to a second end beyond an outer edge of the first antenna structure.

8. The integrated circuit of claim 1, wherein a top-most one of the first conductive lines has an upper surface that is exposed by an opening to form a contact pad.

9. The integrated circuit of claim 8, wherein one of said first conductive lines other than the top most one extends into the active circuit area.

10. The integrated circuit of claim 8, wherein one of said first conductive lines other than the top most one extends into the scribe line.

11. The integrated circuit of claim 1, further comprising a plurality of spaced apart trench regions in the substrate, said trench regions extending perpendicular to the scribe line and extending from a first end located in active circuit area to a second end beyond an outer edge of the first antenna structure.

12. The integrated circuit of claim 11, wherein said trench regions are filled with an insulating material.

13. The integrated circuit of claim 1, further comprising a second antenna structure formed by a second antenna line arranged in said different planes, said first and second antenna structures forming a transformer.

14. The integrated circuit of claim 13, wherein said second antenna line includes a fourth line portion positioned between the pillar structures of the seal ring structure and the scribe line and a fifth line portion positioned between the pillar structures of the seal ring structure and the active circuit area.

15. The integrated circuit of claim 14, wherein said second antenna line further comprises a sixth line portion electrically interconnecting the third line portion to the fourth line portion, said sixth line portion positioned between adjacent ones of the pillar structures.

16. The integrated circuit of claim 13, wherein said first and second antenna structures are formed in different ones of the planes.

17. The integrated circuit of claim 1, wherein the pillar structures are arranged in pairs of pillar structures, and ones of the first conductive lines of the pillar structures of each pair are electrically connected to each other by an intermediate conductive line.

18. The integrated circuit of claim 1, wherein a top-most one of the first conductive lines for each pillar structure of at least a pair of pillar structures are electrically connected to form a contact pad having a top surface exposed by an opening.

19. The integrated circuit of claim 18, wherein at least a portion of the first antenna line of the first antenna structures extends underneath the contact pad.

20. The integrated circuit of claim 1, wherein the first antenna line is interrupted in correspondence with a cutting area for realizing at least one pair of terminals of said first antenna structure.

21. The integrated circuit of claim 1, further comprising a trench structure realized in a central portion of said scribe line.

22. The integrated circuit of claim 21, wherein said trench structure penetrates in said scribe line up to at least the level of said substrate.

23. The integrated circuit of claim 21, wherein said trench structure penetrates in said scribe line and at least partially in said substrate.

24. The integrated circuit of claim 21, wherein said trench structure is covered by a protective layer.

25. The integrated circuit of claim 1, further comprising, adjacent to said first antenna structure, at least one trench comprising at least one material having magnetic features for realizing a magnetic trench.

26. The integrated circuit of claim 25, further comprising at least one pair of magnetic trenches realized on the opposite part with respect to said antenna.

27. The integrated circuit of claim 26, further comprising a further insulating trench realized in said substrate below said first antenna structure and below said magnetic trenches.

28. The integrated circuit of claim 27, further comprising insulating and/or magnetic trenches, inside or around said further insulating trench.

29. The integrated circuit of claim 1, wherein the first antenna line is formed by a plurality of coils connected in series.

30. The integrated circuit of claim 29, wherein the plurality of coils are arranged and electrically connected such that a length of the first antenna structure develops in a vertical direction perpendicular to the substrate in said planes.