Integrated RF front end system

• US 9,419,073 B2
• Filed: 05/04/2015
• Issued: 08/16/2016
• Est. Priority Date: 06/28/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: McPartlin, Michael Joseph, Doherty, Mark M.
• Primary Examiner(s): NGUYEN, TUAN HOANG
• Application Number:
  US14/703,465
• Publication Number:
  US 20150340429A1
• Time in Patent Office: 470 Days
• Field of Search: 455/290, 455/311, 455/333, 455/550.1, 257/379, 257/565, 257/607, 257/656, 257/E29.109, 257/E29.174, 361/718, 361/719, 361/748, 361/760, 361/764, 438/309
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/067 Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0823 including vertical bipolar transistors only
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0821 : Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0826 : Pedestal collectors
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66242 : Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/737 : Hetero-junction transistors
• CPC Class Codes: H01L 29/7371 : Vertical transistors
• CPC Class Codes: H01L 29/7378 : comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01Q 1/24 : with receiving set
• CPC Class Codes: H03F 2200/222 : A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/318 : A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only

Abstract

Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Claims

1. A front-end module (FEM) comprising:

a silicon substrate including a high-resistivity portion;

a bipolar transistor disposed on the substrate above the high-resistivity portion; and

a low-resistivity well located between the bipolar transistor and a passive device, the low-resistivity well providing at least partial electrical isolation between the bipolar transistor and the passive device.

2. The FEM of claim 1 wherein the bipolar transistor includes a silicon base.

3. The FEM of claim 1 wherein the bipolar transistor includes a silicon-germanium alloy base.

4. The FEM of claim 1 wherein the passive device is disposed on the silicon substrate above the high-resistivity portion.

5. The FEM of claim 1 wherein the low-resistivity well surrounds the bipolar transistor.

6. The FEM of claim 1 wherein the silicon substrate further includes a low-resistivity portion.

7. The FEM of claim 6 wherein the low-resistivity portion includes the low-resistivity well.

8. The FEM of claim 1 further comprising a power amplifier, the power amplifier including the bipolar transistor.

9. The FEM of claim 1 wherein the high-resistivity portion has a resistivity of greater than or equal to 1 kOhm*cm.

10. A semiconductor die comprising:

a silicon substrate including a high-resistivity portion, the silicon substrate supporting a plurality of devices including a first device, the first device being a transistor;

front-end circuitry disposed on the silicon substrate, the front-end circuitry including the transistor, the transistor disposed above the high-resistivity portion; and

a low-resistivity well located between the transistor and a second device from the plurality of devices, the low-resistivity well providing at least partial electrical isolation between the transistor and the second device.

11. The semiconductor die of claim 10 wherein at least some of the plurality of devices are passive devices.

12. The semiconductor die of claim 10 wherein the transistor includes one of a silicon base or a silicon-germanium alloy base.

13. The semiconductor die of claim 10 wherein the low-resistivity well surrounds the transistor.

14. The semiconductor die of claim 10 wherein the silicon substrate further includes a low-resistivity portion, the low-resistivity portion including the low-resistivity well.

15. The semiconductor die of claim 10 wherein the high-resistivity portion has a resistivity of greater than or equal to 500 Ohm*cm.

16. A wireless device comprising:

a semiconductor die including a silicon substrate, front-end circuitry, and a low-resistivity well, the silicon substrate including a high-resistivity portion and supporting a plurality of devices including a transistor, the front-end circuitry disposed on the silicon substrate and including the transistor, the transistor disposed above the high-resistivity portion, and a low-resistivity well located between the transistor and an additional device from the plurality of devices, the low-resistivity well providing at least partial electrical isolation between the transistor and the additional device; and

an antenna in electrical communication with the semiconductor die for receiving and transmitting wireless signals.

17. The wireless device of claim 16 wherein at least some of the plurality of devices are passive devices.

18. The wireless device of claim 16 wherein the high-resistivity portion has a resistivity of at least 500 Ohm*cm.

19. The wireless device of claim 16 wherein the low-resistivity well at least partially surrounds the transistor.

20. The wireless device of claim 16 wherein the silicon substrate further includes a low-resistivity portion, the low-resistivity portion including the low-resistivity well.