Lateral devices containing permanent charge

• US 9,419,085 B2
• Filed: 11/09/2015
• Issued: 08/16/2016
• Est. Priority Date: 07/30/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Paul, Amit
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US14/936,526
• Publication Number:
  US 20160172452A1
• Time in Patent Office: 281 Days
• Field of Search: 257/122, 257/141, 257/331, 257/335, 257/336, 257/339, 257/343, 257/408, 257/409, 257/493
• US Class Current: 1/1
• CPC Class Codes: H01L 21/263 with high-energy radiation H01L21/261 takes precedence
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.

Claims

1. A lateral semiconductor device, comprising:

a first-conductivity-type source region;

a second-conductivity-type body region, interposed between said source region and a first-conductivity-type drift region, said body region being capacitively coupled to a gate electrode lying at least partially in a trench;

a first-conductivity-type drain region;

permanent charge embedded in an insulating region which vertically adjoins said drift region, said permanent charge having a polarity which tends to deplete adjacent semiconductor material;

wherein said gate electrode is separated from the adjacent semiconductor material by a layer of gate oxide; and

wherein the gate oxide adjacent to said drift region is thicker than the gate oxide adjacent to said body region.

2. The lateral semiconductor device of claim 1, further comprising a second-conductivity-type semiconductor substrate under said drift region.

3. The lateral semiconductor device of claim 1, further comprising a second-conductivity-type body contact region adjacent to said source region and said body region.

4. The lateral semiconductor device of claim 1, wherein said first conductivity type is N-type.

5. The lateral semiconductor device of claim 1, wherein said permanent charge comprises cesium ions.

6. The lateral semiconductor device of claim 1, wherein the lateral semiconductor device consists primarily of silicon.

7. A lateral semiconductor device, comprising:

a first-conductivity-type source region;

a second conductivity type body region which is interposed between said source region and a first-conductivity-type drift region;

a trench gate which is laterally interposed between said source region and at least a portion of said drift region, and which is capacitively coupled to said body region;

a first gate oxide layer between said body region and said trench gate;

a second gate oxide layer separating said trench gate region;

a second-conductivity-type buried region in said drift region;

permanent charges, embedded in an insulating region which vertically joins second drift region, having a polarity which tends to deplete adjacent portions of said drift region; and

a first-conductivity-type drain region.

8. The lateral semiconductor device of claim 7, further comprising a second-conductivity-type semiconductors substrate under said drift region.

9. The lateral semiconductor device of claim 7, further comprising a second-conductivity-type body contact region adjacent to said source region and said body region.

10. The lateral semiconductor device of claim 7, wherein said first conductivity type is N-type.

11. The lateral semiconductor device of claim 7, wherein said permanent charge comprises cesium ions.

12. The lateral semiconductor device of claim 7, wherein the lateral semiconductor device consists primarily of silicon.

13. A lateral semiconductor device, comprising:

a first-conductivity-type source region;

a second-conductivity-type body region which is interposed between said source region and a first-conductivity-type drift region;

a trench gate, capacitively coupled to said body region, which laterally separates said source region and said body region from at least a portion of said drift region;

a first gate oxide layer which separates said trench gate from said source region and said body region, and a second gate oxide layer which separates said trench gate from said drift region;

wherein said second gate oxide layer is thicker than said first gate oxide layer;

a second-conductivity-type buried region in said drift region;

a second-conductivity-type surface region on the surface of said drift region;

wherein said surface region and said buried region are laterally interposed between said source region and a first-conductivity-type drain region; and

permanent charge, embedded in an insulating region which vertically adjoins at least a portion of said surface region, having a polarity which tends to invert adjacent portions of said surface region.

14. The lateral semiconductor device of claim 13, further comprising a second-conductivity-type semiconductors substrate under said drift region.

15. The lateral semiconductor device of claim 13, further comprising a second-conductivity-type body contact region adjacent to said source region and said body region.

16. The lateral semiconductor device of claim 13, wherein said first conductivity type is N-type.

17. The lateral semiconductor device of claim 13, wherein said permanent charge comprises cesium ions.

18. The lateral semiconductor device of claim 13, wherein the lateral semiconductor device consists primarily of silicon.