Semiconductor device, and manufacturing method for same

• US 9,419,117 B2
• Filed: 07/30/2012
• Issued: 08/16/2016
• Est. Priority Date: 08/02/2011
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Aketa, Masatoshi, Nakano, Yuki
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): AMER, MOUNIR S
• Application Number:
  US14/236,567
• Publication Number:
  US 20140225126A1
• Time in Patent Office: 1,478 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02634 Homoepitaxy
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 : the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/4917 : Crossed wires
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/49844 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0716 : in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/0619 : with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0661 : specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 : Surface layout
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0804 : Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 : Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0834 : Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0865 : Disposition
• CPC Class Codes: H01L 29/1004 : Base region of bipolar transistors
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 : Silicon carbide
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/47 : Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/6606 : the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 : the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66325 : controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66333 : Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7393 : Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 : Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 : and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H02P 27/06 : using dc to ac converters or inverters H02P27/05 takes precedence

Abstract

The present invention is directed to a semiconductor device including a semiconductor chip formed with an SiC-IGBT including an SiC semiconductor layer, a first conductive-type collector region formed such that the collector region is exposed on a second surface of the SiC semiconductor layer, a second conductive-type base region formed such that the base region is in contact with the collector region, a first conductive-type channel region formed such that the channel region is in contact with the base region, a second conductive-type emitter region formed such that the emitter region is in contact with the channel region to define a portion of a first surface of the SiC semiconductor layer, a collector electrode connected to the collector region, and an emitter electrode connected to the emitter region, and a MOSFET including a second conductive-type source region electrically connected to the emitter electrode and a second conductive-type drain region electrically connected to the collector electrode, the MOSFET connected in parallel to the SiC-IGBT.

Claims

1. A semiconductor device comprising:

a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including;

an SiC semiconductor layer having a first surface and a second surface,

a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,

a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,

a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,

a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,

a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and

an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and

a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including;

a second conductive-type source region electrically connected to the emitter electrode; and

a second conductive-type drain region electrically connected to the collector electrode, wherein

the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,

the source region is formed utilizing the emitter region of the SiC-IGBT,

the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,

the collector electrode is collectively connected to the drain region and the collector region,

the SiC semiconductor layer includes;

a second conductive-type SiC substrate defining the second surface of the SiC semiconductor layer and selectively formed with a trench from the second surface toward the first surface, and

a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, wherein

the drain region is formed utilizing the SiC substrate, and

the collector region is formed at the bottom surface of the trench.

2. The semiconductor device according to claim 1, wherein a plurality of the trenches are formed in a striped manner.

3. The semiconductor device according to claim 1, wherein a deepest portion of the trench reaches the interface between the SiC substrate and the SiC base layer.

4. A semiconductor device comprising:

a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including;

an SiC semiconductor layer having a first surface and a second surface,

a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,

a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,

a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,

a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,

a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and

an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and

a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including;

a second conductive-type source region electrically connected to the emitter electrode; and

a second conductive-type drain region electrically connected to the collector electrode, wherein

the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,

the source region is formed utilizing the emitter region of the SiC-IGBT,

the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,

the collector electrode is collectively connected to the drain region and the collector region,

the SiC semiconductor layer includes;

a first conductive-type SiC substrate defining the second surface of the SiC semiconductor layer and selectively formed with a trench from the second surface toward the first surface, and

a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, wherein

the collector region is formed utilizing the SiC substrate, and

the drain region is formed at the bottom surface of the trench.

5. A semiconductor device comprising:

a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including;

an SiC semiconductor layer having a first surface and a second surface,

a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,

a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,

a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,

a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,

a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and

an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and

a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including;

a second conductive-type source region electrically connected to the emitter electrode; and

a second conductive-type drain region electrically connected to the collector electrode, wherein

the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,

the source region is formed utilizing the emitter region of the SiC-IGBT,

the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,

the collector electrode is collectively connected to the drain region and the collector region,

the SiC semiconductor layer includes;

an SiC substrate defining the second surface of the SiC semiconductor layer and having a first conductive-type portion and a second conductive-type portion segmented such that the first and second conductive-type portions are exposed separately on the second surface, and

a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, wherein

the collector region is formed utilizing the first conductive-type portion of the SiC substrate, and

the drain region is formed utilizing the second conductive-type portion of the SiC substrate.

6. The semiconductor device according to claim 5, wherein a plurality of the first conductive-type portions and the second conductive-type portions of the SiC substrate are formed alternately in a striped manner.

7. A semiconductor device comprising:

a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including;

an SiC semiconductor layer having a first surface and a second surface,

a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,

a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,

a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,

a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,

a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and

an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and

a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including;

a second conductive-type source region electrically connected to the emitter electrode; and

a second conductive-type drain region electrically connected to the collector electrode, wherein

the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,

the source region is formed utilizing the emitter region of the SiC-IGBT,

the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,

the collector electrode is collectively connected to the drain region and the collector region,

the SiC semiconductor layer includes;

a second conductive-type SiC substrate defining the second surface of the SiC semiconductor layer and selectively formed with a trench from the second surface toward the first surface, and

a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, wherein

the drain region and the collector region are formed at the bottom surface of the trench in a manner adjacent to each other.

8. A semiconductor device comprising:

a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including;

an SiC semiconductor layer having a first surface and a second surface,

a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,

a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,

a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,

a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,

a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and

an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and

a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including;

a second conductive-type source region electrically connected to the emitter electrode; and

a second conductive-type drain region electrically connected to the collector electrode, wherein

the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,

the source region is formed utilizing the emitter region of the SiC-IGBT,

the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,

the collector electrode is collectively connected to the drain region and the collector region, and

the base region includes a drift region having a first impurity concentration in contact with the channel region and a buffer region formed such that the buffer region surrounds the collector region between the drift region and the collector region and having a second impurity concentration higher than the first impurity concentration.

9. The semiconductor device according to claim 8, wherein

the SiC semiconductor layer includes:

a second conductive-type SiC substrate defining the second surface of the SiC semiconductor layer; and

a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, wherein

a trench penetrating from the second surface of the SiC substrate through the SiC substrate to reach the SiC base layer is selectively formed, and wherein

the drain region is formed utilizing the SiC substrate,

the collector region is formed at the bottom surface of the trench, and

the SiC base layer includes;

a second conductive-type buffer layer formed such that the buffer layer surrounds the collector region to serve as the buffer region; and

a second conductive-type drift layer formed on the buffer layer to serve as the drift region.

10. The semiconductor device according to claim 8, wherein

the SiC semiconductor layer includes:

an SiC substrate defining the second surface of the SiC semiconductor layer and having a first conductive-type portion and a second conductive-type portion segmented such that the first and second conductive-type portions are exposed separately on the second surface; and

a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, and wherein

the collector region is formed utilizing the first conductive-type portion of the SiC substrate,

the drain region is formed utilizing the second conductive-type portion of the SiC substrate, and

the SiC base layer includes;

a second conductive-type buffer layer formed on the SiC substrate such that the buffer layer covers the drain region and the collector region to serve as the buffer region; and

a second conductive-type drift layer formed on the buffer layer to serve as the drift region.