Semiconductor device including switching devices in an epitaxial layer

• US 9,419,127 B2
• Filed: 04/07/2014
• Issued: 08/16/2016
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Takaishi, Masaru
• Primary Examiner(s): Campbell, Shaun
• Assistant Examiner(s): CIESLEWICZ, ANETA B
• Application Number:
  US14/246,675
• Publication Number:
  US 20140231906A1
• Time in Patent Office: 862 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes switching devices in an epitaxial layer on a silicon substrate. Diffusion regions of different conductivity types are provided. In some instances, an electrode layer makes ohmic contact with the epitaxial layer and extends to, and makes ohmic contact with, a diffusion region electrically connected to the epitaxial layer. In some instances, diffusion regions of different conductivity types are arranged alternately one by one outward away from the epitaxial layer side.

Claims

1. A semiconductor device comprising:

a silicon substrate of one conductivity type;

an epitaxial layer of the one conductivity type provided on the silicon substrate;

a first region of an inverse conductivity type provided on the silicon substrate so as to be in direct contact with both the epitaxial layer and the silicon substrate; and

a plurality of switching devices provided in the epitaxial layer,

wherein a first diffusion region of one conductivity type electrically connected to the epitaxial layer is formed in an upper region within the first region opposite from the silicon substrate, wherein

an electrode layer which makes ohmic contact with the epitaxial layer is formed above the epitaxial layer,

the electrode layer extends to reach, and makes ohmic contact with, the first diffusion region electrically connected to the epitaxial layer, and

the epitaxial layer and the first diffusion region are electrically connected to each other via the electrode layer.

2. The semiconductor device according to claim 1, wherein

a trench in which a gate electrode is embedded is formed in the epitaxial layer, and

as seen in a sectional view, a width of the first region is larger than a width of the trench.

3. The semiconductor device according to claim 1, wherein

a trench in which a gate electrode is embedded is formed in the epitaxial layer, and

the gate electrode is embedded so as to fill the trench halfway across a depth thereof.

4. The semiconductor device according to claim 3, wherein an interlayer insulator film is embedded in a remaining part of the trench where the gate electrode is not embedded.

5. The semiconductor device according to claim 4, wherein an upper surface of the interlayer insulator film embedded in the trench is flush with an upper surface of the epitaxial layer.

6. A semiconductor device comprising:

a silicon substrate of one conductivity type;

an epitaxial layer of the one conductivity type provided on the silicon substrate;

a first region of an inverse conductivity type provided on the silicon substrate so as to be in direct contact with both the epitaxial layer and the silicon substrate; and

a plurality of switching devices provided in the epitaxial layer,

wherein a first diffusion region of the one conductivity type electrically connected to the epitaxial layer is formed in an upper region within the first region opposite from the silicon substrate, wherein

a plurality of first diffusion regions of the one conductivity type and a plurality of second diffusion regions of the inverse conductivity type are formed in the first region,

the plurality of first diffusion regions and the plurality of second diffusion regions are arranged alternately one by one from an epitaxial layer side outward away from the epitaxial layer side, with one of the first diffusion regions located at an innermost position closest to the epitaxial layer, and

the first diffusion region located at the innermost position is the first diffusion region electrically connected to the epitaxial layer.

7. The semiconductor device according to claim 6, wherein

the switching devices provided in the epitaxial layer include a gate electrode, and

one of the plurality of first diffusion regions located between the second diffusion regions is electrically connected to the gate electrode.

8. The semiconductor device according to claim 6, wherein

the plurality of first diffusion regions and the plurality of second diffusion regions are so arranged that one of the first diffusion regions is located at an outermost position farthest away from the epitaxial layer, and

the first diffusion region located at the outermost position is electrically connected to the silicon substrate.

9. The semiconductor device according to claim 8, further comprising a second region of the one conductivity type provided on the silicon substrate and arranged outside the first region opposite from the epitaxial layer, wherein

the first diffusion region located at the outermost position is formed so as to extend from the first region to the second region, and is electrically connected via the second region to the silicon substrate.

10. The semiconductor device according to claim 6, wherein the plurality of first diffusion regions and the plurality of second diffusion regions are formed so as to surround the epitaxial layer.

11. The semiconductor device according to claim 6, wherein

the plurality of first diffusion regions and the plurality of second diffusion regions are diffusion regions formed by injecting an impurity into the first region from an upper surface side thereof, and

a thickness of the plurality of second diffusion regions from an upper surface of the first region is larger than a thickness of the plurality of first diffusion regions from the upper surface of the first region.

12. The semiconductor device according to claim 6, wherein

a trench in which a gate electrode is embedded is formed in the epitaxial layer, and

as seen in a sectional view, a width of the first region is larger than a width of the trench.

13. The semiconductor device according to claim 6, wherein

a trench in which a gate electrode is embedded is formed in the epitaxial layer, and

the gate electrode is embedded so as to fill the trench halfway across a depth thereof.

14. The semiconductor device according to claim 13, wherein an interlayer insulator film is embedded in a remaining part of the trench where the gate electrode is not embedded.

15. The semiconductor device according to claim 14, wherein an upper surface of the interlayer insulator film embedded in the trench is flush with an upper surface of the epitaxial layer.