Split gate semiconductor device with curved gate oxide profile

• US 9,419,129 B2
• Filed: 10/21/2009
• Issued: 08/16/2016
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Gao, Yang, Chen, Kuo-In, Terrill, Kyle, Shi, Sharon
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US12/603,028
• Publication Number:
  US 20110089485A1
• Time in Patent Office: 2,491 Days
• Field of Search: 257/330, 257/331, 257/332, 257/E21.41, 257/E29.262, 438/259, 438/270, 438/271, 438/589
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.

Claims

1. A semiconductor device comprising:

a source region;

a drain region; and

a trench gate formed within a trench-like region, said trench gate comprising;

a first layer comprising a thermal oxide layer and a first dielectric layer, wherein said thermal oxide layer is along the bottom surface and sidewall surfaces of said trench-like region, and wherein said first dielectric layer is over said thermal oxide layer;

a first electrode region adjacent said first dielectric layer, wherein the height of said first layer is less than the height of said first electrode region;

a second dielectric layer adjacent said first dielectric layer and said first electrode region, said second dielectric layer having a uniform composition throughout;

a gate oxide layer adjacent said second dielectric layer, wherein the boundary of said gate oxide layer and said second dielectric layer is curved; and

a second electrode region adjacent said gate oxide layer.

2. The semiconductor device of claim 1 wherein said first electrode region and said second electrode region comprise polysilicon.

3. The semiconductor device of claim 1 wherein said boundary is concave relative to said second dielectric layer and convex relative to said gate oxide layer.

4. The semiconductor device of claim 1 wherein said first dielectric layer and said second dielectric layer each comprises sub-atmospheric undoped silicon glass (SAUSG).

5. The semiconductor device of claim 1 comprising a power metal oxide semiconductor field effect transistor (MOSFET) device.

6. The semiconductor device of claim 1 wherein said gate oxide layer also separates said second electrode region from said source region.

13. The semiconductor device of claim 1 wherein said gate oxide layer also separates said second electrode region from said source region.

7. A semiconductor device comprising:

a source region;

a drain region; and

a gate formed within a trench-like region within said semiconductor device, wherein said gate comprises;

a thermal oxide layer lining the bottom of said trench-like region and extending to a height only partially up the sidewalls of said trench-like region;

a first dielectric region adjacent said thermal oxide layer and extending to a height that does not exceed said height of said thermal oxide layer;

a first electrode region adjacent said first dielectric region, wherein the height of said thermal oxide layer and said first dielectric region is less than the height of said first electrode region;

a second electrode region above said first electrode region in said trench-like region; and

a second dielectric region adjacent said thermal oxide layer, said first dielectric region, and said first electrode region, said second dielectric region having a uniform composition throughout and also having a surface that traverses the entire width of said trench-like region between said first and second electrode regions, wherein said surface is concave.

8. The semiconductor device of claim 7 wherein said first electrode region and said second electrode region comprise polysilicon.

9. The semiconductor device of claim 7 further comprising a gate oxide layer that separates said second dielectric region from said second electrode region.

10. The semiconductor device of claim 9 wherein said second dielectric region separates said first dielectric region from said gate oxide layer.

11. The semiconductor device of claim 7 wherein said first dielectric region and said second dielectric region each comprises sub-atmospheric undoped silicon glass (SAUSG).

12. The semiconductor device of claim 7 comprising a power metal oxide semiconductor field effect transistor (MOSFET) device.