Semiconductor device and method for manufacturing the same

• US 9,419,146 B2
• Filed: 01/22/2013
• Issued: 08/16/2016
• Est. Priority Date: 01/26/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Reames, Matthew
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US13/746,793
• Publication Number:
  US 20130193431A1
• Time in Patent Office: 1,302 Days
• Field of Search: 257/43, 257/51, 257/64, 257/47, 257/57, 438/106, 438/104, 438/166, 438486-487
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02672 using crystallisation enhancing elements
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.

Claims

1. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating film over the gate electrode layer;

an oxide semiconductor layer over the gate insulating film;

an insulating layer over the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer over the insulating layer,

wherein the oxide semiconductor layer comprises;

a first region which overlaps with the insulating layer;

a second region which is in contact and overlaps with the source electrode layer; and

a third region which is in contact and overlaps with the drain electrode layer,

wherein the first region is positioned between the second region and the third region,

wherein a crystallinity of the first region is higher than a crystallinity of each of the second region and the third region,

wherein a defect density of the first region is lower than a defect density of the second region,

wherein the first region comprises a first crystal part and a second crystal part,

wherein a c-axis of each of the first crystal part and the second crystal part is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer,

wherein directions of an a-axis and a b-axis of the first crystal part are different from directions of an a-axis and a b-axis of the second crystal part,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and

wherein the insulating layer is in direct contact with top and side surfaces of the oxide semiconductor layer.

2. The semiconductor device according to claim 1,

wherein a hydrogen concentration of the first region is lower than a hydrogen concentration of each of the second region and the third region.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer further comprises:

a fourth region which is in contact and overlaps with the insulating layer; and

a fifth region which is in contact and overlaps with the insulating layer,

wherein the second region and the third region are positioned between the fourth region and the fifth region, and

wherein the crystallinity of the first region is same as a crystallinity of each of the fourth region and the fifth region.

4. The semiconductor device according to claim 1,

wherein at least one of the source electrode layer and the drain electrode layer is not in contact with an edge portion of the oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises:

a first oxide semiconductor film which is in contact with the gate insulating film; and

a second oxide semiconductor film which is in contact with the source electrode layer, the drain electrode layer, and the insulating layer,

wherein an indium concentration of the first oxide semiconductor film is higher than an indium concentration of the second oxide semiconductor film, and

wherein a gallium concentration of the second oxide semiconductor film is higher than a gallium concentration of the first oxide semiconductor film.

6. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises:

a first oxide semiconductor film which is in contact with the gate insulating film; and

a second oxide semiconductor film which is in contact with the source electrode layer, the drain electrode layer, and the insulating layer,

wherein an indium concentration of the first oxide semiconductor film is higher than a gallium concentration of the first oxide semiconductor film, and

wherein a gallium concentration of the second oxide semiconductor film is higher than an indium concentration of the second oxide semiconductor film.

7. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises:

a first oxide semiconductor film which is in contact with the gate insulating film; and

a second oxide semiconductor film which is in contact with the source electrode layer, the drain electrode layer, and the insulating layer,

wherein an indium concentration of the first oxide semiconductor film is higher than an indium concentration of the second oxide semiconductor film,

wherein a gallium concentration of the second oxide semiconductor film is higher than a gallium concentration of the first oxide semiconductor film,

wherein the indium concentration of the first oxide semiconductor film is higher than the gallium concentration of the first oxide semiconductor film, and

wherein the gallium concentration of the second oxide semiconductor film is higher than the indium concentration of the second oxide semiconductor film.

8. The semiconductor device according to claim 1,

wherein the insulating layer comprises an aluminum oxide film.

9. A semiconductor device comprising:

an oxide semiconductor layer over a substrate;

a gate insulating film over the oxide semiconductor layer;

a gate electrode layer over the gate insulating film; and

a source electrode layer and a drain electrode layer over the oxide semiconductor layer,

wherein the oxide semiconductor layer comprises;

a first region which overlaps with the gate electrode layer;

a second region which does not overlap with the gate electrode layer; and

a third region which does not overlap with the gate electrode layer;

wherein the first region is positioned between the second region and the third region,

wherein a crystallinity of the first region is higher than a crystallinity of each of the second region and the third region,

wherein a defect density of the first region is lower than a defect density of the second region,

wherein the first region comprises a first crystal part and a second crystal part,

wherein a c-axis of each of the first crystal part and the second crystal part is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer,

wherein directions of an a-axis and a b-axis of the first crystal part are different from directions of an a-axis and a b-axis of the second crystal part,

wherein the oxide semiconductor layer comprises indium, gallium, and zinc, and

wherein the gate insulating film is in direct contact with top and side surfaces of the oxide semiconductor layer.

10. The semiconductor device according to claim 9,

wherein a hydrogen concentration of each of the second region and the third region is higher than a hydrogen concentration of the first region.

11. The semiconductor device according to claim 9,

wherein the source electrode layer and the drain electrode layer are positioned over the gate insulating film, and

wherein the source electrode layer and the drain electrode layer are electrically connected to the second region and the third region, respectively.

12. The semiconductor device according to claim 9, further comprising sidewalls on side surfaces of the gate electrode layer.

13. The semiconductor device according to claim 9,

wherein the oxide semiconductor layer further comprises:

a fourth region which is in contact and overlaps with the source electrode layer; and

a fifth region which is in contact and overlaps with the drain electrode layer,

wherein the second region and the third region are positioned between the fourth region and the fifth region,

wherein a hydrogen concentration of each of the second region and the third region is higher than a hydrogen concentration of each of the fourth region and the fifth region, and

wherein the gate insulating film is positioned over the source electrode layer and the drain electrode layer.

14. The semiconductor device according to claim 9,

wherein each of the source electrode layer and the drain electrode layer is in contact with an edge portion of the oxide semiconductor layer.