Process-compensated HBT power amplifier bias circuits and methods

• US 9,419,567 B2
• Filed: 06/13/2013
• Issued: 08/16/2016
• Est. Priority Date: 06/14/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Ripley, David Steven, Lehtola, Philip John, Zampardi, Peter J. Jr., Shao, Hongxiao, Ko, Tin Myint, Ozalas, Matthew Thomas
• Primary Examiner(s): NGUYEN, HIEU P
• Application Number:
  US13/917,552
• Publication Number:
  US 20130344825A1
• Time in Patent Office: 1,160 Days
• Field of Search: 330/289, 330/285, 330/296, 330/256, 330/266, 330/272
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0658 Vertical bipolar transistor in combination with resistors or capacitors
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/7304 the device being a resistive element, e.g. ballasting resistor transistors integrated with resistors H01L27/075
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/8605 Resistors with PN junctions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/18 : the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/318 : A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/411 : the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/555 : A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/21 : with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/213 : in integrated circuits
• CPC Class Codes: H04B 1/3827 : Portable transceivers
• CPC Class Codes: H04B 1/40 : Circuits

Abstract

The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

Claims

1. A system for biasing a power amplifier, the system comprising:

a first die including a power amplifier circuit, a semiconductor resistor, and an isolation feature, the power amplifier circuit including a transistor formed on a semiconductor, the semiconductor resistor formed from one or more layers as a layer stack device on the semiconductor that includes the transistor, the isolation feature configured to isolate the semiconductor resistor from the transistor, the semiconductor resistor configured to sense a beta parameter of the power amplifier circuit, the beta parameter dependent on characteristics of the first die; and

a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on a measurement of the beta parameter sensed by the semiconductor resistor of the first die.

2. The system of claim 1 wherein the first die includes a heterojunction bipolar transistor (HBT) die, and the second die includes a silicon die.

3. The system of claim 2 wherein the semiconductor resistor is formed from a portion of the HBT die.

4. The system of claim 3 wherein the semiconductor resistor is formed from a base material of the HBT die.

5. The system of claim 1 wherein the semiconductor resistor has a resistance value that is approximately proportional to a temperature of the first die.

6. The system of claim 3 wherein the bias signal generating circuit includes a V-I circuit configured to provide a reference current to the semiconductor resistor, the reference current having a value that depends on the resistance of the semiconductor resistor.

7. The system of claim 6 wherein the V-I circuit provides the reference current based on a PTAT reference voltage that is substantially independent of the one or more conditions of the first die.

8. The system of claim 6 wherein the V-I circuit is further configured to generate the bias signal based on the reference current drawn by the semiconductor resistor.

17. The system of claim 1 wherein the semiconductor resistor is a substitute for a thin-film resistor.

9. A wireless device comprising:

a transceiver configured to process RF signals;

an antenna in communication with the transceiver configured to facilitate transmission of an amplified RF signal;

a power amplifier including a transistor formed on a semiconductor of a first die, the power amplifier connected to the transceiver and configured to generate the amplified RF signal, the first die including a semiconductor resistor and an isolation feature, the semiconductor resistor formed from one or more layers as a layer stack device on the semiconductor that includes the transistor, the isolation feature configured to isolate the semiconductor resistor from the transistor, the semiconductor resistor configured to sense a beta parameter of the power amplifier, the beta parameter dependent on characteristics of the first die; and

a bias circuit disposed on a second die and interconnected to the power amplifier, the bias circuit configured to generate a bias signal for the power amplifier based at least in part on a measurement of the beta parameter sensed by the semiconductor resistor of the first die.

18. The wireless device of claim 9 wherein the semiconductor resistor is a substitute for a thin-film resistor.

10. A power amplifier module comprising:

a packaging substrate configured to receive a plurality of components;

a first die mounted on the packaging substrate, the first die including a power amplifier circuit, a semiconductor resistor, and an isolation feature, the power amplifier circuit including a transistor formed on a semiconductor, the semiconductor resistor formed from one or more layers as a layer stack device on the semiconductor that includes the transistor, the isolation feature configured to isolate the semiconductor resistor from the transistor, the semiconductor resistor configured to sense a beta parameter of the power amplifier circuit, the beta parameter dependent on characteristics of the first die; and

a second die mounted on the packaging substrate and interconnected with the first die, the second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on a measurement of the beta parameter sensed by the semiconductor resistor of the first die.

11. The power amplifier module of claim 10 wherein the first die includes a III-V semiconductor die mounted on the packaging substrate, the first die including an HBT having a selected layer above a sub-collector layer, the semiconductor resistor having a resistive layer disposed laterally from, and electrically isolated from the selected layer, the resistive layer and the selected layer formed from substantially the same material.

12. The power amplifier module of claim 11 wherein the selected layer includes a base layer.

13. The power amplifier module of claim 11 wherein the selected layer includes a sub-collector layer.

14. The power amplifier module of claim 11 wherein the semiconductor resistor further includes electrical contact pads disposed on the resistive layer to yield a resistance value for the semiconductor resistor.

15. The power amplifier module of claim 11 wherein the semiconductor resistor is connected to a circuit located outside of the first die.

16. The power amplifier module of claim 11 wherein the semiconductor resistor is configured to be sensitive to a change in one or more conditions associated with the selected layer of the HBT.