In-situ delay element calibration

• US 9,419,598 B2
• Filed: 11/12/2014
• Issued: 08/16/2016
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Palmer, Robert E., Bucher, Michael D., Fuller, Andrew M.
• Primary Examiner(s): LUU, AN T
• Application Number:
  US14/539,564
• Publication Number:
  US 20150145581A1
• Time in Patent Office: 643 Days
• Field of Search: 327/261, 327/263, 327276-278, 327/280, 327/291, 327/298
• US Class Current: 1/1
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.

Claims

1. A controllable delay element, comprising:

a delay element to provide a variable delay to an input signal to generate an output signal, the variable delay to be controlled by a digital delay input, the delay element to have a delay range of the variable delay between a first delay to be set by a first value of the digital delay input and a second delay to be set by a second value of the digital delay input, the first delay and the second delay to be referenced to a same edge of the output signal; and

,

a delay range control circuit to control the delay range in response to a delay range input.

2. The controllable delay element of claim 1, further comprising:

a delay range calibration circuit to set the delay range input in response to a relative delay between a first timing reference and a second timing reference.

3. The controllable delay element of claim 2, wherein the delay range calibration circuit is to set the delay range input to minimize a difference between the second delay and the relative delay between the first timing reference and the second timing reference.

4. The controllable delay element of claim 2, wherein the first timing reference is to be received as the input signal and a delay between a received first timing reference and the second timing reference signal is to be adjusted to minimize a first timing difference between the output signal and the received first timing reference signal.

5. The controllable delay element of claim 4, wherein the delay range calibration circuit is to adjust the delay range input to minimize a second timing difference between the output signal and the received first timing reference signal while the second value is received by the digital delay input.

6. The controllable delay element of claim 5, wherein the delay between the received first timing reference and the second timing reference signal is to be adjusted to minimize the first delay between the output signal and the received first timing reference signal while the first value is received by the digital delay input.

7. The controllable delay element of claim 6, wherein the first value corresponds to the delay element providing a minimum delay and the second value corresponds to the delay element providing a maximum delay.

8. A method of calibrating a delay element, comprising:

receiving a first timing reference and a second timing reference while the first timing reference and the second timing reference have a first relative delay between the first timing reference and the second timing reference;

applying the first timing reference to a signal input of a digitally controlled delay element, the digitally controlled delay element providing a variable delay to the first timing reference to generate an output signal, the variable delay controlled by a digital delay input, the delay element having an adjustable delay range of the variable delay between a first delay set by a first value of the digital delay input and a second delay set by a second value of the digital delay input, the delay range set by a delay range input; and

,

adjusting the delay range input to minimize a delay between the output signal and the second timing reference.

9. The method of claim 8, further comprising:

receiving the first timing reference and the second timing reference while the first timing reference and the second timing reference have a second relative delay between the first timing reference and the second timing reference; and

,

adjusting, from the second relative delay, a relative timing of the first timing reference and the second timing reference to minimize a timing difference between the output signal and the second timing reference.

10. The method of claim 9, wherein the delay range input is set to produce a minimum adjustable delay range while the relative timing of the first timing reference and the second timing reference are adjusted to minimize a timing difference between the output signal and the second timing reference.

11. The method of claim 9, wherein the first value corresponds to the delay element providing a minimum delay and the second value corresponds to the delay element providing a maximum delay.

12. The method of claim 11, wherein the delay range input is adjusted to minimize a timing difference between the output signal and the second timing reference while the digital delay input is set at the second value.

13. The method of claim 9, further comprising:

receiving a third timing reference at a plurality of digitally controlled variable delay elements of a respective plurality of receivers, a respective delay of each of the plurality of digitally controlled variable delay elements each controlled by a respective first digital input value;

receiving the third timing reference at a digitally controlled variable delay element of a strobe receiver, a delay of the digitally controlled variable delay element of the strobe receiver controlled by a second digital input value; and

,

measuring a relative delay of each of the respective delay of each of the plurality of digitally controlled variable delay elements while each of the respective first digital input values are set at a predetermined value, the relative delay of each of the respective delay of each of the plurality of digitally controlled variable delay elements measured by varying the second digital input value and detecting a state of a respective sampler of each of the respective plurality of receivers for a plurality of digital input values.

14. An interface, comprising:

a strobe receiver including a first delay element to provide a first variable delay to an input timing reference signal to generate an output timing reference signal, the first variable delay to be controlled by a first delay input value; and

,

a plurality of input receivers each including second delay elements to provide a plurality of second variable delays to the input timing reference signal to generate a respective output that is provided as an input to a respective sampler that is to be clocked by the output timing reference signal, the respective second variable delays to be controlled by respective second delay input values, the outputs of the respective samplers providing indicators of a respective relative timing of the respective second variable delays.

15. The interface of claim 14, wherein the indicators of respective relative timing of the respective second variable delays are used to determine a first delay input value.

16. The interface of claim 14, wherein a plurality of first delay input values are used to measure a plurality of respective relative timings of the second variable delays each associated with an input receiver of the plurality of input receivers.

17. The interface of claim 16, wherein the plurality of first delay input values are used to measure the plurality of respective relative timings of the second variable delays while the respective second delay input values are each set to a predetermined value.

18. The interface of claim 17, wherein the predetermined value is associated with a midpoint delay that can be provided by the second delay elements.

19. The interface of claim 14, wherein a plurality of first delay input values are used to measure a plurality of respective relative timings of the second variable delays each associated with an input receiver of the plurality of input receivers, the plurality of respective relative timings including a maximum measured timing and a minimum measure timing.

20. The interface of claim 19, wherein the first delay input value is set based on the maximum measured timing and the minimum measure timing.