Data transfer clock recovery for legacy systems
First Claim
1. A deserializer circuit comprising:
- a sampler circuit configured to receive a stream of bits transmitted at a transmission rate and sample the received stream of bits at a reception rate higher than the transmission rate;
a symbol assembly circuit coupled with the sampler circuit, and configured to group a portion of the sampled stream of bits into a frame; and
a bit alignment circuit coupled with the symbol assembly circuit, and the bit alignment circuit configured to detect a frame slip when two sampled bits within the frame have different values, and upon detecting the frame slip, the bit alignment circuit configured to realign the frame until the two sampled bits share a same bit value representing a data bit output of the received stream of bits.
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Accused Products
Abstract
The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate serial data, the receiver having a jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the SERDES receiver for frame realignment; and supplying to an output of the SERDES receiver one of the bits of said same value from each frame at the low data rate.
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Citations
20 Claims
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1. A deserializer circuit comprising:
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a sampler circuit configured to receive a stream of bits transmitted at a transmission rate and sample the received stream of bits at a reception rate higher than the transmission rate; a symbol assembly circuit coupled with the sampler circuit, and configured to group a portion of the sampled stream of bits into a frame; and a bit alignment circuit coupled with the symbol assembly circuit, and the bit alignment circuit configured to detect a frame slip when two sampled bits within the frame have different values, and upon detecting the frame slip, the bit alignment circuit configured to realign the frame until the two sampled bits share a same bit value representing a data bit output of the received stream of bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 15, 16)
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12. A deserializer circuit comprising:
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a symbol assembly circuit configured to collect a stream of received bits into a frame having a frame length of bits; and a bit alignment circuit including; a data frame register coupled with the symbol assembly to receive the frame of received bits, the data frame register having a mid-frame bit and a peripheral bit configured to store two received bits of the frame length of bits; and a comparator circuit coupled with the data frame register to receive the mid-frame bit and the peripheral bit, the comparator circuit configured to generate a jog signal when the mid-frame bit is different from the peripheral bit, the jog signal causing the data frame register to realign the frame until the mid-frame bit and the peripheral bit share a same data bit representing an output data bit of the stream of received bits. - View Dependent Claims (13, 14)
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17. A bit alignment circuit for use in a deserializer configured to sample a stream of bits, the bit alignment circuit comprising:
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a data frame register configured to store a frame length of sampled bits having a mid-frame bit and a peripheral bit; and a comparator circuit coupled with the data frame register to receive the mid-frame bit and the peripheral bit, the comparator circuit configured to generate a jog signal when the mid-frame bit is different from the peripheral bit, the jog signal causing the data frame register to realign the frame until the mid-frame bit and the peripheral bit share a same bit value representing an output data bit of the sampled bits. - View Dependent Claims (18, 19, 20)
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Specification