Camera system dual-encoder architecture
First Claim
1. A camera system, comprising:
- an image sensor chip configured to produce image data representative of light incident upon the image sensor chip;
an image signal processor chip (“
ISP”
) configured to process the image data; and
an image capture accelerator chip (“
ICA”
) coupled between the image sensor chip and the ISP, the image capture accelerator comprising;
an input configured to receive the image data from the image sensor chip;
an H.264 encoder configured to encode the received image data to produce a set of frames, the set of frames comprising a set of i-frames, a set of b-frames, and a set of p-frames,a wavelet encoder configured to encode the set of i-frames to produce a set of encoded i-frames;
a concatenator configured to concatenate the set of encoded i-frames, the set of b-frames, and the set of p-frames to produce concatenated encoded image data; and
an output configured to output the received image data when the ICA is configured to operate in a normal mode and to output the concatenated encoded image data when the ICA is configured to operate in an accelerated mode.
4 Assignments
0 Petitions
Accused Products
Abstract
An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.
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Citations
20 Claims
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1. A camera system, comprising:
-
an image sensor chip configured to produce image data representative of light incident upon the image sensor chip; an image signal processor chip (“
ISP”
) configured to process the image data; andan image capture accelerator chip (“
ICA”
) coupled between the image sensor chip and the ISP, the image capture accelerator comprising;an input configured to receive the image data from the image sensor chip; an H.264 encoder configured to encode the received image data to produce a set of frames, the set of frames comprising a set of i-frames, a set of b-frames, and a set of p-frames, a wavelet encoder configured to encode the set of i-frames to produce a set of encoded i-frames; a concatenator configured to concatenate the set of encoded i-frames, the set of b-frames, and the set of p-frames to produce concatenated encoded image data; and an output configured to output the received image data when the ICA is configured to operate in a normal mode and to output the concatenated encoded image data when the ICA is configured to operate in an accelerated mode. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for capturing images by a camera system, comprising:
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capturing, by an image sensor chip, light incident upon the image sensor to produce image data representative of the captured light; encoding, by an H.264 encoder of an image capture accelerator chip (“
ICA”
) coupled to the image sensor chip, the received image data to produce a set of frames, the set of frames comprising a set of i-frames, a set of b-frames, and a set of p-frames;encoding, by a wavelet encoder of the ICA, the set of i-frames to produce a set of encoded i-frames; concatenating the set of encoded i-frames, the set of b-frames, and the set p-frames to produce concatenated encoded image data; when the ICA is configured to operate in a normal mode, outputting the received image data; and when the ICA is configured to operate in an accelerated mode, outputting the concatenated encoded image data. - View Dependent Claims (9, 10, 11, 12, 13)
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14. An image capture accelerator integrated circuit (“
- ICA”
), comprising;an input configured to receive the image data captured by an image sensor chip; an H.264 encoder configured to encode the received image data to produce a set of frames, the set of frames comprising a set of i-frames, a set of b-frames, and a set of p-frames; a wavelet encoder configured to encode the set of i-frames to produce a set of encoded i-frames; a concatenator configured to concatenate the set of encoded i-frames, the set of b-frames, and the set of p-frames to produce concatenated encoded image data; and an output configured to output the received image data when the ICA is configured to operate in a normal mode and to output the concatenated encoded image data when the ICA is configured to operate in an accelerated mode. - View Dependent Claims (15, 16, 17, 18, 19, 20)
- ICA”
Specification