Method to enhance programming performance in multilevel NVM devices

• US 9,423,961 B2
• Filed: 09/08/2014
• Issued: 08/23/2016
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Levy, Atai, Kasorla, Yoav, Mouler, Stas, Borisenkov, Alex, Koyfman, Dmitry
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): CHRZANOWSKI, MATTHEW R
• Application Number:
  US14/479,732
• Publication Number:
  US 20160070473A1
• Time in Patent Office: 715 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

An apparatus includes an interface and a processor. The interface is configured to communicate with a memory device. The processor is configured to send to the memory device, via the interface, a sequence of write commands that program multiple types of memory pages that incur respective different programming durations in the memory device, while inserting in the sequence suspension periods for permitting execution of storage commands that are not part of the sequence, such that at least some of the suspension periods are followed by write commands of types that do not have a shortest programming duration among the programming durations.

Claims

1. Apparatus comprising:

an interface, which is configured to communicate with a memory device; and

a processor, which is configured to send to the memory device, via the interface, a sequence of write commands that program multiple types of memory pages that incur respective different programming durations in the memory device, while inserting, in the sequence, suspension periods for permitting execution of storage commands that are not part of the sequence, such that at least some of the suspension periods are followed by write commands of types that do not have a shortest programming duration among the programming durations.

2. The apparatus according to claim 1, wherein the processor is configured to execute, during the suspension periods, at least one storage command that is not part of the sequence.

3. The apparatus according to claim 2, wherein the interface is configured to communicate with one or more additional memory devices, and wherein the processor is configured to execute the storage command that is not part of the sequence in the additional memory devices.

4. The apparatus according to claim 2, wherein the storage command that is not part of the sequence comprises a read command.

5. The apparatus according to claim 1, wherein the multiple types comprise a Least Significant Bit (LSB) page type and at least one additional page type, and wherein the processor is configured to insert at least some of the suspension periods before write commands of the additional page type.

6. The apparatus according to claim 1, wherein the processor is configured to send the write commands in a cache programming mode.

7. A method, comprising:

sending to a memory device a sequence of write commands that program multiple types of memory pages that incur respective different programming durations in the memory device; and

inserting, in the sequence, suspension periods for permitting execution of storage commands that are not part of the sequence, such that at least some of the suspension periods are followed by write commands of types that do not have a shortest programming duration among the programming durations.

8. The method according to claim 7, and comprising executing, during the suspension periods, at least one storage command that is not part of the sequence.

9. The method according to claim 8, wherein executing the storage command comprises performing the storage command that is not part of the sequence in one or more additional memory devices.

10. The method according to claim 8, wherein the storage command that is not part of the sequence comprises a read command.

11. The method according to claim 7, wherein the multiple types comprise a Least Significant Bit (LSB) page type and at least one additional page type, and wherein inserting the suspension periods comprises inserting at least some of the suspension periods before write commands of the additional page type.

12. The method according to claim 7, wherein sending the sequence comprises sending the write commands in a cache programming mode.

13. Apparatus comprising:

a memory device; and

a processor, which is configured to send to the memory device, via an interface, a sequence of write commands that program multiple types of memory pages that incur respective different programming durations in the memory device, while inserting, in the sequence, suspension periods for permitting execution of storage commands that are not part of the sequence, such that at least some of the suspension periods are followed by write commands of types that do not have a shortest programming duration among the programming durations.

14. The apparatus according to claim 13, wherein the processor is configured to execute, during the suspension periods, at least one storage command that is not part of the sequence.

15. The apparatus according to claim 14, wherein the processor is configured to execute the storage command that is not part of the sequence in one or more additional memory devices.

16. The apparatus according to claim 14, wherein the storage command that is not part of the sequence comprises a read command.

17. The apparatus according to claim 13, wherein the multiple types comprise a Least Significant Bit (LSB) page type and at least one additional page type, and wherein the processor is configured to insert at least some of the suspension periods before write commands of the additional page type.

18. The apparatus according to claim 13, wherein the processor is configured to send the write commands in a cache programming mode.