Design, layout, and manufacturing techniques for multivariant integrated circuits

• US 9,424,383 B2
• Filed: 01/25/2014
• Issued: 08/23/2016
• Est. Priority Date: 04/11/2011
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kelleher, Brian
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/164,173
• Publication Number:
  US 20140143742A1
• Time in Patent Office: 941 Days
• Field of Search: 716/51, 716 54- 56
• US Class Current: 1/1
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Claims

1. A method comprising:

designing an integrated circuit including a plurality of variants, wherein one integrated circuit variant includes a plurality of modular circuits communicatively coupled together and a second integrated circuit variant includes a sub-set of the plurality of modular circuits;

laying out the plurality of variants of the integrated circuit for wafer fabrication, wherein the layout includes primary scribe boundaries separating each set of the plurality of modular circuits of the first variant and secondary scribe boundaries separating the sub-set of the plurality of modular circuits of the second variant from the other modular circuits in the first variant, and wherein the layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last;

fabricating the integrated circuit on a wafer according to the layout up to but not including fabricating the one or more metallization layers to be fabricated last;

predicting a demand for each of the integrated circuit variants during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last;

selecting one or more of the plurality of variants of the integrated circuit based upon the predicted demand;

fabricating the last one or more metallization layers to include a subset of the communicative couplings of the integrated circuit according to the layout of the selected one or more variants of the integrated circuit; and

singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more variants of the integrated circuit.

2. The method according to claim 1, wherein predicting the demand comprises a market analysis of the demand for each of the plurality of variants.

3. The method according to claim 1, further comprising:

estimating a yield for each of the plurality of variants during fabrication of the integrated circuit up to but not including the one or more metallization layers to be fabricated last; and

selecting the one or more of the plurality of variants of the integrated circuit further based upon the estimated yield.

4. The method according to claim 1, further comprising:

predicting an initial demand for each of the plurality of variants before fabricating the integrated circuit up to but not including the one or more metallization layers to be fabricated last; and

fabricating the integrated circuit according to the layout and the initial predicted demand up to but not including the one or more metallization layers to be fabricated last.

5. The method according to claim 1, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and a demand; and

laying out the plurality of variants of the integrated circuit based on the market analysis.

6. The method according to claim 1, further comprising:

packaging the plurality of integrated circuit die into integrated circuit chips of the selected one or more variants; and

shipping the integrated circuit chips of the selected one or more variants.

7. The method according to claim 1, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and a demand; and

designing the integrated circuit including the plurality of variants based on the market analysis.