SRAM cell layout structure and devices therefrom

• US 9,424,385 B1
• Filed: 10/10/2014
• Issued: 08/23/2016
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Tien, George, Kidd, David A., Clark, Lawrence T.
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US14/511,487
• Time in Patent Office: 683 Days
• Field of Search: 716/55, 716/119, 716/122
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A method for modifying a design of an integrated circuit includes obtaining design layout data for the integrated circuit and selecting at least one SRAM cell in the integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer. The method also includes extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout. The method further includes adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the SRAM cell and altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal.

Claims

1. A method for fabricating an integrated circuit, comprising:

extracting, from design layout data for the integrated circuit, active area patterns associated with the least one SRAM cell in the integrated circuit to be defined using an enhanced body effect (EBE) NMOS active area layout and an EBE PMOS active area layout, the design layout including at least one notch;

adjusting a size of the active area patterns in the EBE NMOS active area layout to reduce a width of at least pull-down devices in the at least one SRAM cell;

altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal; and

after the adjusting and altering, forming the EBE NMOS active areas, EBE PMOS active areas, and the gate layer on a substrate based on the EBE NMOS active area layout, the EBE PMOS active area layout, and the gate layer layout, the forming comprising selecting the EBE NMOS active areas and the EBE PMOS active areas to comprise a substantially undoped channel layer and a highly doped screening region beneath the channel layer.

2. The method of claim 1, further comprising:

prior to said forming, selecting process parameters such that electrical parameters for transistors in the at least one SRAM cell meet a criteria, the selection of the process parameters based at least on the EBE NMOS active area layout, the EBE PMOS active area layout, and the gate layer layout.

3. The method of claim 1, wherein the step of adjusting comprises resizing a portion of the EBE NMOS active area layout so that a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell are substantially equal.

4. The method of claim 3, wherein the resizing comprises reducing the width of the pull-down devices and removing notches from the existing design layout.

5. The method of claim 1, wherein the step of altering comprises resizing the gate layer layout for the pull-up devices and removing notches from the existing design layout.

6. The method of claim 1, wherein the step of adjusting further comprises resizing the EBE NMOS active areas so that at least one overall dimension of the at least one SRAM cell is reduced.

7. The method of claim 1, wherein the reducing comprises reducing a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell.

8. The method of claim 1, wherein the step of altering comprises resizing the gate layer layout for the pull-down devices and removing notches from the existing design layout.

9. A method for producing an integrated circuit mask, comprising:

converting a base integrated circuit design layout with at least one SRAM cell to a layout utilizing enhanced body effect (EBE) transistors, with the EBE transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer with the conversion module;

dividing at NMOS and PMOS active area patterns in the design layout into at least one enhanced body effect EBE active area layout with the at NMOS and PMOS active area patterns for the at least one SRAM;

adjusting a size of the NMOS active area patterns in the EBE NMOS active area layout to reduce a width of at least pull-down devices in the at least one SRAM cell;

altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal; and

after the adjusting and the altering, forming the integrated circuit mask comprising the NMOS and PMOS active area patterns and the gate layer layout.

10. The method of claim 9, further comprising:

after the altering and adjusting, selecting process parameters such that electrical parameters for transistors in the at least one SRAM cell meet a criteria, the selection of the process parameters based at least on the EBE NMOS active area layout, the EBE PMOS active area layout, and the gate layer layout.

11. The method of claim 9, wherein the step of adjusting comprises resizing a portion of the EBE NMOS active area layout associated with the pull-down devices so that a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell are substantially equal, wherein the step of altering comprises resizing the gate layer layout for the pull-up devices.

12. The method of claim 9, wherein the step of adjusting comprises resizing a portion of the EBE NMOS active area layout associated with the pull-down devices so that a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell are substantially equal, wherein the step of altering comprises resizing the gate layer layout for the pull-up devices, and wherein the step of adjusting further comprises reducing a width of the EBE NMOS active areas so that at least one overall dimension of the at least one SRAM cell is reduced.

13. The method of claim 9, wherein the step of altering comprises resizing the gate layer layout for the pull-down devices, and wherein the step of adjust comprises reducing widths of the pulldown devices and pass-gate devices in the at least one SRAM cell so that one overall dimension of the at least one SRAM cell is reduced.

14. A method for providing a layout design of an integrated circuit, comprising:

obtaining design layout data for a base integrated circuit;

selecting at least one SRAM cell in the base integrated circuit to utilize enhanced body effect (EBE) transistors comprising a substantially undoped channel layer and a highly doped screening region beneath the channel layer;

extracting, from the design layout, NMOS active area patterns and PMOS active area patterns associated with the least one SRAM cell to define an EBE NMOS active area layout and a EBE PMOS active area layout;

adjusting the EBE NMOS active area layout to reduce a width of at least pull-down devices in the at least one SRAM cell; and

altering a gate layer layout in the design layout data such that a length of pull-up devices in the at least one SRAM and a length of the pull-down devices are substantially equal;

after the adjusting and the altering, forming the layout design of an integrated circuit comprising the EBE NMOS active area layout, the EBE PMOS active area layout and the gate layer layout.

15. The method of claim 14, wherein the step of adjusting comprises resizing a portion of the EBE NMOS active area layout so that a width of the pull-down devices and a width of pass-gate devices in the at least one SRAM cell are substantially equal.

16. The method of claim 14, wherein the step of adjusting further comprises resizing of the NMOS active area patterns so that at least one overall dimension of the at least one SRAM cell is reduced.

17. The method of claim 14, further comprising the step of resizing the gate layer layout for the pulldown devices.