Method and system for fast initialization of a memory unit

• US 9,424,896 B2
• Filed: 06/22/2012
• Issued: 08/23/2016
• Est. Priority Date: 06/22/2012
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Groot, Cas, Storms, Maurits
• Primary Examiner(s): Chen, Xuxing
• Application Number:
  US13/531,297
• Publication Number:
  US 20130346733A1
• Time in Patent Office: 1,523 Days
• Field of Search: 713/1
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Embodiments of a method for operating a computer system are disclosed. In one embodiment, the memory unit has a non-volatile memory array and processing logic and the non-volatile memory array stores initialization data that is used by the processing logic to perform input/output operations of the memory unit. The method involves storing the initialization data in retention registers within the memory unit, wherein the retention registers are separate from the non-volatile memory array and retain data while the memory unit is power gated, using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating.

Claims

1. A method of operating a memory unit of a computer system, the memory unit having a non-volatile memory array and processing logic, wherein the non-volatile memory array stores initialization data that is used by the processing logic to perform input/output operations of the memory unit, the method comprising:

storing the initialization data in retention registers within the memory unit, wherein the retention registers are separate from the non-volatile memory array and retain data while the memory unit is power gated; and

using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating and determining that this is not a cold start;

wherein using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating comprises populating volatile registers of the processing logic with the initialization data; and

wherein the initialization data comprises trimming data, wherein the trimming data is stored in the retention registers and wherein the initialization data that is populated in the volatile registers of the processing logic from the retention registers includes the trimming data and the trimming data is used by the processing logic to perform input/output operations upon exiting the power gating.

2. The method of claim 1 wherein the initialization data comprises redundancy data, wherein using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating comprises populating volatile registers of the processing logic with the redundancy data, wherein the redundancy data is stored in the retention registers and wherein the redundancy data that is populated in the volatile registers of the processing logic from the retention registers is used by the processing logic to perform input/output operations upon exiting the power gating.

3. The method of claim 1 wherein the initialization data comprises security data.

4. A method of operating a memory unit of a computer system, the memory unit having a non-volatile memory array and processing logic, wherein the non-volatile memory array stores trimming data that is used by the processing logic to perform input/output operations of the memory unit, the method comprising:

powering up the memory unit;

reading the trimming data from the non-volatile memory array;

storing the trimming data in retention registers of the memory unit;

populating volatile registers of the processing logic with the trimming data;

power gating the memory unit such that the trimming data is no longer stored in the volatile registers of the processing logic;

powering up the memory unit after the power gating;

populating the volatile registers of the processing logic with the trimming data stored in the retention registers instead of with the trimming data stored in the non-volatile memory array;

performing input/output operations using the trimming data populated in the volatile registers of the processing logic upon powering up the memory unit after the power gating.

5. The method of claim 4 wherein redundancy data is also stored in the retention registers and used to populate the volatile registers of the processing logic upon powering up the memory unit after the power gating.

6. A memory unit comprising:

a non-volatile memory array, wherein the non-volatile memory array stores trimming data;

processing logic configured to perform input/output operations of the memory unit, wherein the processing logic includes volatile registers for storing the trimming data when the memory unit is in a normal operating mode;

retention registers configured to store data even when the memory unit is power gated from a power source;

a controller configured to;

store the trimming data in the retention registers; and

populate the volatile registers of the processing logic using the trimming data from the retention registers upon transition from a low power mode to the normal operating mode.

7. The memory unit of claim 6 further comprising a power switch configured to power gate the memory unit from a power source.

8. The memory unit of claim 6 wherein memory unit input/output operations are performed in the normal operating mode and no memory unit input/output operations are performed in the low power mode.

9. A computer system comprising:

a memory unit, the memory unit comprising;

a non-volatile memory array, wherein the non-volatile memory array stores initialization data, wherein the initialization data comprises at least one of trimming data and redundancy data,

processing logic configured to perform input/output operations of the memory unit, wherein the processing logic includes volatile registers for storing the initialization data when the memory unit is in a normal operating mode,

retention registers configured to store data even when the memory unit is power gated from a power source, and

a controller configured to;

store the initialization data in the retention registers, and

populate the volatile registers of the processing logic using the initialization data from the retention registers upon transition from a low power mode to the normal operating mode, wherein the volatile registers of the processing logic are populated using the initialization data from the retention registers instead of from the non-volatile memory array upon transition from a low power mode to a normal operating mode

a microprocessor;

a data bus that connects the microprocessor to the memory unit;

a power management unit connected to provide power to the memory unit; and

a power switch, in a power transmission path between the memory unit and the power management unit, configured to power gate the memory unit from the power management unit in a low power mode.

10. The computer system of claim 9 wherein the microprocessor and memory unit are fabricated on the same substrate.

11. The computer system of claim 9 wherein the microprocessor and memory unit are fabricated on different substrates and packaged in a multi-die package.

12. The computer system of claim 9, wherein the initialization data is stored in the retention registers upon cold start of the computer system.