Static ram

• US 9,424,912 B2
• Filed: 05/26/2015
• Issued: 08/23/2016
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Wu, Wenhao
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US14/721,343
• Publication Number:
  US 20150380081A1
• Time in Patent Office: 455 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A static RAM includes: a plurality of memory cells provided at intersections of bit line pairs and word lines; a write driver connected between a high potential power source line and a drive line; a column switch including a first transistor pair which connects one of the plurality of bit line pairs to the write driver; and a boost circuit which boosts the drive line to a negative potential, wherein the boost circuit includes: a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and a boost control transistor connected between the drive line and a reference potential power source line, the boost signal is applied to a gate of the boost control transistor, and the threshold value of the boost control transistor is lower than the threshold value of the first transistor pair.

Claims

1. A static RAM comprising:

a plurality of word lines;

a plurality of bit line pairs;

a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines;

a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line;

a column switch including a first transistor pair which connects one of the plurality of bit line pairs, which is selected, to the write driver; and

a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of write of a memory cell of the plurality of memory cells, wherein

the boost circuit includes;

a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and

a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied, and

a threshold value of the boost control transistor is lower than a threshold value of the first transistor pair.

2. The static RAM according to claim 1, wherein

each memory cell of the plurality of memory cells includes a second transistor pair that connects the each memory cell to the bit line pair, and

the threshold value of the boost control transistor is lower than a threshold value of the second transistor.

3. A static RAM comprising:

a plurality of word lines;

a plurality of bit line pairs;

a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines, including a first transistor pair which is selected by the word line and which transfers data with the bit line pair;

a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line;

a column switch which selects one of the plurality of bit line pairs and which connects the selected bit line pair to the write driver; and

a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of write of a memory cell of the plurality of memory cells, wherein

the boost circuit includes;

a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and

a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied, and

a threshold value of the boost control transistor is lower than a threshold value of the first transistor pair.

4. A static RAM comprising:

a plurality of word lines;

a plurality of bit line pairs;

a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines;

a write driver connected between a high potential power source line whose potential is higher than a reference potential, and a drive line;

a column switch including a first transistor pair which connects one of the plurality of bit line pairs, which is selected, to the write driver; and

a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of write of a memory cell of the plurality of memory cells, wherein

the boost circuit includes;

a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied;

a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied; and

an over-boost limitation transistor connected between the drive line and the reference potential power source line, and

a threshold value of the over-boost limitation transistor is lower than a threshold value of the first transistor pair.

5. The static RAM according to claim 4, wherein

each memory cell of the plurality of memory cells includes a second transistor pair which connects the each memory cell to the bit line pair, and the threshold value of the over-boost limitation transistor is lower than a threshold value of the second transistor.

6. A static RAM comprising:

a plurality of word lines;

a plurality of bit line pairs;

a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines, and including a first transistor pair which is selected by the word line and which transfers data with the bit line pair;

a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line;

a column switch which selects one of the plurality of bit line pairs and which connects the selected bit line pair to the write driver; and

a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at the time of write of a memory cell of the plurality of memory cells, wherein

the boost circuit includes;

a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which, a boost signal is applied;

a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied; and

an over-boost limitation transistor connected between the drive line and the reference potential power source line, and

a threshold value of the over-boost limitation transistor is lower than a threshold value of the first transistor pair.