Mechanisms for semiconductor device structure

• US 9,425,048 B2
• Filed: 11/06/2013
• Issued: 08/23/2016
• Est. Priority Date: 11/06/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Hsin-Ying, Wang, Mei-Yun, Wang, Hsien-Cheng, Yang, Fu-Kai, Liu, Shih-Wen, Hsu, Audrey Hsiao-Chiu
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US14/073,408
• Publication Number:
  US 20150123175A1
• Time in Patent Office: 1,021 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0334 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. Formation of voids, which tend to be formed in a rectangular hard mask structure, is prevented. In addition, formation of a self-aligned contact in the semiconductor device becomes easier, and risks of shortage between the contact and a metal gate structure in the semiconductor device decreased. In addition, a method for forming the semiconductor device structure is also provided. The method may include a gate last process.

Claims

1. A semiconductor device structure, comprising:

a substrate;

a metal gate structure formed over the substrate;

a spacer comprising an inner side and an outermost side, wherein the inner side is closer to the metal gate structure than the outermost side, wherein the inner side is formed on the metal gate structure; and

a funnel shaped hard mask structure formed over and directly aligned with the metal gate structure, wherein a portion of a top surface of the funnel shaped hard mask structure extends horizontally past the outmost side of the spacer.

2. The semiconductor device structure as claimed in claim 1, further comprising:

a contact formed over the substrate, wherein a sidewall of the contact is adjacent to an edge of a top surface of the funnel shaped hard mask structure.

3. The semiconductor device structure as claimed in claim 1, wherein the funnel shaped hard mask structure has a cone-shaped top portion and a tube-shaped bottom portion.

4. The semiconductor device structure as claimed in claim 1, wherein a top surface of the funnel shaped hard mask structure has a first width in a range from 12 nm to 200 nm.

5. The semiconductor device structure as claimed in claim 1, wherein a bottom surface of the funnel shaped hard mask structure has a second width in a range from 10 nm to 200 nm.

6. The semiconductor device structure as claimed in claim 1, wherein a thickness of the funnel shaped hard mask structure is in a range from 10 nm to 50 nm.

7. The semiconductor device structure as claimed in claim 1, wherein an angle between a top surface and a sidewall of the funnel shaped hard mask structure is in a range from 30°

to 75°

.

8. The semiconductor device structure as claimed in claim 1, wherein the funnel shaped hard mask structure is made of silicon nitride.

9. The semiconductor device structure as claimed in claim 3, wherein an angle between a sidewall of the cone-shaped top portion and a sidewall of the tube-shaped bottom portion is in a range from 120°

to 165°

.

10. A semiconductor device structure, comprising:

a substrate;

a metal gate structure formed over the substrate;

a spacer comprising an inner side and an outermost side, wherein the inner side is closer to the metal gate structure than the outermost side, wherein the inner side is formed on the metal gate structure;

a funnel shaped hard mask structure formed over and directly aligned with the metal gate structure, wherein a portion of a top surface of the funnel shaped hard mask structure extends horizontally past the outmost side of the spacer, wherein the funnel shaped hard mask structure is made of silicon nitride; and

a self-aligned contact formed over the substrate.

11. The semiconductor device structure as claimed in claim 10, wherein the funnel shaped hard mask structure has a cone-shaped top portion and a tube-shaped bottom portion.

12. The semiconductor device structure as claimed in claim 10, wherein a thickness of the funnel shaped hard mask structure is in a range of 10 nm to 50 nm.

13. The semiconductor device structure as claimed in claim 10, wherein an angle between a top surface and a sidewall of the funnel shaped hard mask structure is in a range from 30°

to 75°

.

14. The semiconductor device structure as claimed in claim 10, wherein the first width is in a range from 12 nm to 200 nm.

15. The semiconductor device structure as claimed in claim 10, the second width is in a range from 10 nm to 200 nm.

16. The semiconductor device structure as claimed in claim 11, wherein an angle between a sidewall of the cone-shaped top portion and a sidewall of the tube-shaped bottom portion is in a range from 120°

to 165°

.