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Complementary metal oxide semiconductor device and method of manufacturing the same

  • US 9,425,104 B2
  • Filed: 04/23/2014
  • Issued: 08/23/2016
  • Est. Priority Date: 09/06/2013
  • Status: Active Grant
First Claim
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1. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device, the method comprising:

  • forming a buffer layer directly on a silicon substrate, the buffer layer including at least one of a Group IV and a Group III-V material;

    forming a material layer for an n-type transistor on the buffer layer;

    etching the material layer for the n-type transistor to form a first layer for the n-type transistor and a first pattern;

    forming an insulating layer on the first layer and the first pattern;

    etching the insulating layer to form a second pattern for selective growth, the second pattern exposing the buffer layer;

    selectively growing a second layer for a p-type transistor in the second pattern, the second layer contacting the buffer layer; and

    planarizing the second layer and the insulating layer to expose the first layer;

    wherein the first layer is isolated from the second layer by the insulating layer.

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