Complementary metal oxide semiconductor device and method of manufacturing the same
First Claim
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1. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device, the method comprising:
- forming a buffer layer directly on a silicon substrate, the buffer layer including at least one of a Group IV and a Group III-V material;
forming a material layer for an n-type transistor on the buffer layer;
etching the material layer for the n-type transistor to form a first layer for the n-type transistor and a first pattern;
forming an insulating layer on the first layer and the first pattern;
etching the insulating layer to form a second pattern for selective growth, the second pattern exposing the buffer layer;
selectively growing a second layer for a p-type transistor in the second pattern, the second layer contacting the buffer layer; and
planarizing the second layer and the insulating layer to expose the first layer;
wherein the first layer is isolated from the second layer by the insulating layer.
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Abstract
Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a silicon substrate, and a first layer including a group III-V material is disposed on the buffer layer. A second layer including a group IV material is disposed on the buffer layer or the silicon substrate while being spaced apart from the first layer.
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Citations
17 Claims
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1. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device, the method comprising:
- forming a buffer layer directly on a silicon substrate, the buffer layer including at least one of a Group IV and a Group III-V material;
forming a material layer for an n-type transistor on the buffer layer;
etching the material layer for the n-type transistor to form a first layer for the n-type transistor and a first pattern;
forming an insulating layer on the first layer and the first pattern;
etching the insulating layer to form a second pattern for selective growth, the second pattern exposing the buffer layer;
selectively growing a second layer for a p-type transistor in the second pattern, the second layer contacting the buffer layer; and
planarizing the second layer and the insulating layer to expose the first layer;
wherein the first layer is isolated from the second layer by the insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
- forming a buffer layer directly on a silicon substrate, the buffer layer including at least one of a Group IV and a Group III-V material;
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15. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device, the method comprising:
- forming a buffer layer directly on a substrate, the buffer layer including at least one of a Group IV and a Group III-V material;
forming a first material layer on the buffer layer, the first material layer including a group III-V material;
etching the first material layer and the buffer layer to form a first layer and a first pattern, the first pattern exposing the substrate;
forming an insulating layer on the first layer and the first pattern;
etching the insulating layer to form a second pattern, the second pattern exposing the substrate;
selectively growing a second material layer in the second pattern, the second material layer including a group IV material; and
planarizing the second layer and the insulating layer to expose the first layer;
wherein the first layer is isolated from the second layer by the insulating layer. - View Dependent Claims (16, 17)
- forming a buffer layer directly on a substrate, the buffer layer including at least one of a Group IV and a Group III-V material;
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