Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems

• US 9,425,110 B1
• Filed: 08/27/2015
• Issued: 08/23/2016
• Est. Priority Date: 08/27/2015
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Inventors: Padilla, Jose G., Shih, Shih-En, Hon, Philip W., Tsai, Roger S., Zeng, Xianglin
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US14/837,718
• Time in Patent Office: 362 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6683 for monolithic microwave integrated circuit [MMIC]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/17106 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Claims

1. A wafer level package comprising:

a first wafer substrate including a first surface and a second surface;

a second wafer substrate including a first surface and a second surface, said first wafer substrate being bonded to the second wafer substrate and defining a cavity therebetween;

at least one intercavity interconnect (ICIC) extending across the cavity and being electrically coupled to at least one via extending through the first wafer substrate or the second wafer substrate;

a first integrated circuit fabricated on the second surface of the first substrate and positioned within the cavity;

a second integrated circuit fabricated on the first surface of the second substrate and positioned within the cavity where one of the first and second integrated circuits is designated as an active circuit and the other of the first and second integrated circuits is designated as an inactive circuit; and

a metal blanket layer deposited over the inactive circuit so as to make the inactive circuit inoperable.

2. The package according to claim 1 wherein the first and second integrated circuits are redundant and mirrored circuits and include the same circuit components.

3. The package according to claim 1 wherein the metal blanket layer includes at least one opening through which the at least one ICIC extends to be electrically isolated from the metal layer.

4. The package according to claim 3 wherein the at least one ICIC is electrically coupled to an RF or DC electrical contact formed on the first surface of the first wafer substrate by a via extending through the first wafer substrate.

5. The package according to claim 1 wherein the at least one ICIC is electrically coupled to the metal blanket layer.

6. The package according to claim 1 wherein the at least one ICIC is a plurality of ICICs where at least one of the plurality of ICICs extends through an opening in the metal blanket layer and at least one of the plurality of ICICs is electrically coupled to the metal blanket layer.

7. The package according to claim 1 wherein the first and second integrated circuits are designated as the active circuit or the inactive circuit based on a performance test of the integrated circuit.

8. The package according to claim 7 wherein the performance test includes providing DC and RF measurements of the integrated circuit.

9. A wafer level package comprising:

a first wafer substrate including a first surface and a second surface;

a second wafer substrate including a first surface and a second surface, said first wafer substrate being bonded to the second wafer substrate and defining a cavity therebetween;

a first integrated circuit fabricated on the second surface of the first substrate and positioned within the cavity;

a second integrated circuit fabricated on the first surface of the second substrate and positioned within the cavity where one of the first and second integrated circuits is designated as an active circuit and the other of the first and second integrated circuits is designated as an inactive circuit, wherein the first and second integrated circuits are redundant circuits and include the same circuit components; and

a metal blanket layer deposited over the inactive circuit so as to make the inactive circuit inoperable.

10. The package according to claim 9 further comprising a plurality of intercavity interconnects (ICICs) where at least one of the plurality of ICICs extends through an opening in the metal blanket layer and at least one of the plurality of ICICs is electrically coupled to the metal blanket layer.

11. The package according to claim 9 wherein the first and second integrated circuits are designated as the active circuit or the inactive circuit based on a performance test of the integrated circuit.

12. A method for fabricating a three-dimensional wafer level package including vertically redundant integrated circuits, said method comprising:

providing a plurality of wafer substrates;

fabricating a plurality of integrated circuits on each of the wafer substrates;

testing a performance of each of the integrated circuits on all of the wafer substrates;

generating a wafer map for each of the wafer substrates based on the performance test for each of the integrated circuits on each wafer substrate that identifies each circuit as being an operable active circuit or an inoperable inactive circuit based on its performance;

pairing two or more wafer substrates together based on their respective wafer maps to optimize a yield of pairs of vertically opposed circuits where an optimized number of pairs of integrated circuits includes at least one active circuit;

processing each integrated circuit on each wafer based on the wafer-to-wafer pairing so that the active circuits include active circuit connections and the inactive circuits include a metallization layer that short circuits components in the inactive circuit; and

providing wafer-to-wafer bonding of the wafer substrates that have been paired together so that vertically opposed active and inactive integrated circuits are positioned within a cavity between the wafer substrates.

13. The method according to claim 12 wherein testing the performance of the integrated circuits includes performing one or more of in-circuit measurements of DC and/or RF characteristics, DC and/or RF measurements of strategically placed probeable sample devices, or combinations thereof.

14. The method according to claim 12 wherein pairing two or more wafer substrates includes minimizing the number of inactive circuit pairs.

15. The method according to claim 12 wherein processing each integrated circuit includes exposing each active circuit to an active mask plate to generate the circuit connections and exposing each inactive circuit to an inactive mask plate to provide the metallization layer.

16. The method according to claim 15 wherein the inactive mask plate includes cut-out regions that prevent one or more ports in the inactive circuit from being metalized by the metal layer.

17. The method according to claim 16 wherein processing each integrated circuit includes electrically coupling the ports in the inactive cell to an intercavity interconnect (ICIC) extending across the cavity.

18. The method according to claim 15 wherein the active plate and the inactive plate are about the same size of the integrated circuit.

19. The method according to claim 12 further comprising providing backside and three-dimensional wafer fabrication processes for the plurality of wafer substrates prior to providing wafer-to-wafer bonding.