Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods

• US 9,425,175 B2
• Filed: 01/20/2016
• Issued: 08/23/2016
• Est. Priority Date: 03/14/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Krabe, Detlef Bernd, Wittl, Josef
• Primary Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US15/002,333
• Publication Number:
  US 20160141279A1
• Time in Patent Office: 216 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/005 relating to encapsulations
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/16 : the semiconductor device sensitive to radiation being controlled by the light source or sources
• CPC Class Codes: H01L 31/167 : the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 33/005 : Processes
• CPC Class Codes: H01L 33/52 : Encapsulations
• CPC Class Codes: H01S 5/0201 : Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth
• CPC Class Codes: H01S 5/02325 : Mechanically integrated components on mount members or optical micro-benches
• CPC Class Codes: H01S 5/0237 : by soldering
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10121 : Optical component, e.g. opto-electronic component
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

Embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies and methods of making them are provided. The eWLP methods allow back side electrical and/or thermal connections to be easily and economically made at the eWLP wafer level without having to use thru-mold vias (TMVs) or thru-silicon vias (TSVs) to make such connections. In order to create TMVs, processes such as reactive ion etching or laser drilling followed metallization are needed, which present difficulties and increase costs. In addition, the eWLP methods allow electrical and optical interfaces to be easily and economically formed on the front side and/or on the back side of the eWLP wafer, which allows the eWLP methods to be used to form optoelectronic devices having a variety of useful configurations.

Claims

1. An embedded Wafer-Level Packaging (eWLP) package comprising:

at least first and second chips encapsulated inside of a molded material, the molded material having a front side and a back side, the front side of the molded material being co-planar with respective front sides of the first and second chips, a back side of the molded material being parallel to the front side of the molded material, the first and second chips having respective first electrical contacts disposed on respective front sides of the first and second chips and exposed thru the front side of the molded material, the first chip having at least one second electrical contact disposed on a back side of the first chip; and

a metal layer disposed on the back side of the molded material, the second electrical contact disposed on the back side of the first chip being electrically coupled to the metal layer, the back side of the second chip being in contact with the metal layer, and wherein the second chip comprises a bulk material having a predetermined electrical conductivity that is sufficiently high for conducting electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip.

2. The eWLP package of claim 1, wherein the first chip is an electrical-to-optical converter (EO) chip for converting an electrical signal into an optical signal and wherein the second chip comprises a combination of an EO driver for driving the EO chip and an optical-to-electrical (OE) converter for converting an optical signal received by the second chip into an electrical signal.

3. The eWLP package of claim 2, wherein the EO chip is a light-emitting diode (LED) chip, the EO driver is an LED driver and the OE converter is a photodiode.

4. The eWLP package of claim 2, wherein the EO chip is a laser diode chip, the EO driver is a laser diode driver and the OE converter is a photodiode.

5. The eWLP package of claim 1, wherein a purpose of the second chip is to conduct electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip such that an electrical connection is made via the second chip and the metal layer to said at least one second electrical contact disposed on the back side of the first chip.

6. The eWLP package of claim 1, further comprising:

at least a third chip encapsulated inside of the molded material such that the front side of the molded material is co-planar with a front side of the third chip, the third chip having at least one first electrical contact disposed on the front side thereof and exposed thru the front side of the molded material, the third chip having at least one second electrical contact disposed on a back side of the third chip, and wherein the metal layer disposed on the back side of the molded material is electrically coupled to the second electrical contact disposed on the back side of the third chip.

7. The eWLP package of claim 6, wherein a purpose of the second chip is to conduct electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip such that an electrical connection is made via the second chip and the metal layer to said at least one second electrical contact disposed on the back side of the first chip.

8. The eWLP package of claim 7, wherein the first chip is an optical-to-electrical (OE) converter chip for converting an optical signal into an electrical signal, and wherein the third chip is a receiver chip for processing the electrical signal.

9. The eWLP package of claim 7, wherein the first chip is an electrical-to-optical (EO) converter chip for converting an electrical signal into an optical signal.

10. The eWLP package of claim 9, wherein the EO converter chip is a light-emitting diode (LED) chip.

11. The eWLP package of claim 10, wherein the third chip is an LED driver chip.

12. The eWLP package of claim 9, wherein the EO converter chip is a laser diode chip.

13. The eWLP package of claim 12, wherein the third chip is a laser diode driver chip.

14. The eWLP package of claim 9, wherein the third chip is an optical-to-electrical (OE) converter chip that converts an optical signal received by the OE converter chip into an electrical signal.

15. The eWLP package of claim 14, wherein the OE converter chip is a photodiode chip.

16. The eWLP package of claim 14, wherein the second chip is a receiver chip for processing the electrical signal.

17. An embedded Wafer-Level Packaging (eWLP) package comprising:

at least first, second and third chips encapsulated inside of a molded material, the molded material having a front side and a back side, the front side of the molded material being co-planar with respective front sides of the first, second and third chips, a back side of the molded material being parallel to the front side of the molded material, the first, second and third chips having respective first electrical contacts disposed on respective front sides of the first, second and third chips and exposed thru the front side of the molded material, the first and third chips each having at least one second electrical contact disposed on a back side of the first and third chips; and

a metal layer disposed on the back side of the molded material, the second electrical contacts disposed on the back sides of the first and third chips being electrically coupled to the metal layer, the back side of the second chip being in contact with the metal layer, and wherein the second chip comprises a bulk material having a predetermined electrical conductivity that is sufficiently high for conducting electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip, and wherein a purpose of the second chip is to conduct electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip such that an electrical connection is made via the second chip and the metal layer to said at least one second electrical contact disposed on the back side of the first chip.

18. The eWLP package of claim 17, wherein the first chip is an optical-to-electrical (OE) converter chip for converting an optical signal into an electrical signal, and wherein the third chip is a receiver chip for processing the electrical signal.

19. The eWLP package of claim 17, wherein the first chip is an electrical-to-optical (EO) converter chip for converting an electrical signal into an optical signal.

20. The eWLP package of claim 19, wherein the third chip is an optical-to-electrical (OE) converter chip that converts an optical signal received by the OE converter chip into an electrical signal.

21. An embedded Wafer-Level Packaging (eWLP) assembly comprising:

a circuit board (CB) having a plurality of electrical contacts disposed on a first surface thereof;

an eWLP package comprising;

at least first and second chips encapsulated inside of a molded material, the molded material having a front side and a back side, the front side of the molded material being co-planar with respective front sides of the first and second chips, a back side of the molded material being parallel to the front side of the molded material, the first and second chips having respective first electrical contacts disposed on respective front sides of the first and second chips and exposed thru the front side of the molded material, the first chip having at least one second electrical contact disposed on a back side of the first chip, and

a metal layer disposed on the back side of the molded material, the second electrical contact disposed on the back side of the first chip being electrically coupled to the metal layer, the back side of the second chip being in contact with the metal layer, and wherein the second chip comprises a bulk material having a predetermined electrical conductivity that is sufficiently high for conducting electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip;

and

a plurality of electrically-conductive contact elements, each electrically conductive contact element interconnecting one of the first electrical contacts disposed on the front sides of the first and second chips and one of the electrical contacts disposed on the first surface of the CB.