Non-volatile memory for high rewrite cycles application

• US 9,425,204 B2
• Filed: 05/06/2014
• Issued: 08/23/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Ching, Wen-Hao, Lai, Yen-Hsin, Wang, Shih-Chen
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US14/271,429
• Publication Number:
  US 20150092498A1
• Time in Patent Office: 840 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7882 charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND

Abstract

A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.

Claims

1. A non-volatile memory cell comprising:

a coupling device formed on a first well, a second terminal of the coupling device is electrically coupled to a source line;

a read device electrically directly connected to the coupling device, a first terminal of the read device is electrically coupled to a first bit line, a gate of the read device is electrically coupled to a first word line;

a floating gate device formed on a second well;

a program device electrically connected to the floating gate device and formed on the second well, a first terminal of the program device is electrically coupled to a second bit line, a gate of the program device is electrically coupled to a second word line; and

an erase device formed on a third well, a first terminal of the erase device is electrically coupled to an erase line;

wherein the coupling device, the floating gate device and the erase device are coupled by a common floating gate.

2. The non-volatile memory cell of claim 1, wherein the read device is formed on the first well.

3. The non-volatile memory cell of claim 1, wherein the read device is formed on the second well.

4. The non-volatile memory cell of claim 1, wherein a gate of the coupling device is a first part of the common floating gate formed on the first well, a gate of the read device is formed on the first well, and a second terminal of the read device is electrically coupled to a first terminal of the coupling device.

5. The non-volatile memory cell of claim 1, further comprising an assistant device coupled to the coupling device, the floating gate device, and the erase device.

6. The non-volatile memory cell of claim 5, wherein a second terminal of the coupling device is electrically coupled to the assistant device.

7. The non-volatile memory cell of claim 1, wherein a gate of the floating gate device is a second part of the common floating gate formed on the second well, a gate of the program device is formed on the second well, and a second terminal of the program device is electrically coupled to a first terminal of the floating gate device.

8. The non-volatile memory cell of claim 1, wherein a gate of the erase device is a third part of the common floating gate formed on the third well.

9. The non-volatile memory cell of claim 1, wherein the first well and the third well are N-wells formed on a substrate and the second well is a P-well formed on the substrate.

10. The non-volatile memory cell of claim 1, wherein the third well is an N-well formed on a deep N-well formed on a substrate, and the first well and the second well are P-wells formed on the deep N-well.

11. The non-volatile memory cell of claim 1, wherein an area of a gate of the coupling device is larger than an area of a gate of the floating gate device.

12. A memory system having a plurality of the non-volatile memory cells of claim 1, the memory system comprising:

a plurality of the first bit lines each coupled to the first terminals of the read devices of the non-volatile memory cells in a corresponding column;

a plurality of the second bit lines each coupled to the first terminals of the program devices of the non-volatile memory cells in a corresponding column;

a plurality of the first word lines each coupled to the gates of the read devices of the non-volatile memory cells in a corresponding row;

a plurality of the second word lines each coupled to the gates of the program devices of the non-volatile memory cells in a corresponding row;

a plurality of the source lines each coupled to the second terminals of the coupling devices of the non-volatile memory cells in a corresponding row; and

a plurality of the erase lines each coupled to the first terminals of the erase devices of the non-volatile memory cells in a corresponding row.

13. A non-volatile memory cell comprising:

a coupling device formed on a first well;

a read device formed on a second well and electrically directly connected to the coupling device;

a floating gate device formed on the second well;

a program device electrically connected to the floating gate device and formed on the second well; and

an erase device formed on a third well;

wherein the coupling device, the floating gate device and the erase device are coupled by a common floating gate.