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Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology

  • US 9,425,206 B2
  • Filed: 12/23/2014
  • Issued: 08/23/2016
  • Est. Priority Date: 12/23/2014
  • Status: Active Grant
First Claim
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1. An integrated circuit (IC), comprising:

  • a semiconductor substrate comprising a first region and a second region separated by a boundary region;

    a non-volatile memory (NVM) or a poly SiON (silicon oxy-nitride) CMOS device located over the first region;

    a periphery circuit disposed over the second region;

    one or more electrically inactive dummy structures laterally disposed between the NVM or the poly SiON CMOS device and the periphery circuit, wherein a bottom surface of the one or more electrically inactive dummy structures is disposed over a top surface of the semiconductor substrate; and

    a shallow trench isolation (STI) region comprising a first upper surface and a second upper surface that is recessed to a depth in comparison with the first upper surface to provide a recessed portion of the STI region, wherein the recessed portion of the STI region is laterally offset from the one or more electrically inactive dummy structures.

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