Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology

• US 9,425,206 B2
• Filed: 12/23/2014
• Issued: 08/23/2016
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Wu, Wei Cheng, Kao, Ya-Chen, Liu, Shih-Chang, Chu, Fang-Lan
• Primary Examiner(s): Nguyen, Dao H
• Assistant Examiner(s): Nguyen, Tram H
• Application Number:
  US14/580,454
• Publication Number:
  US 20160181268A1
• Time in Patent Office: 609 Days
• Field of Search: 257/314, 257/401, 257/192, 257/369, 257/288, 257/295, 257/351, 257/371, 438/283, 438/591, 438/592, 438/294, 438/400, 438/216, 438/151, 438/154, 438/163, 438/218, 438/221, 438/296, 438/424, 438/585, 438/587, 438/593, 365/185.17, 365/158, 365/163
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

Claims

1. An integrated circuit (IC), comprising:

a semiconductor substrate comprising a first region and a second region separated by a boundary region;

a non-volatile memory (NVM) or a poly SiON (silicon oxy-nitride) CMOS device located over the first region;

a periphery circuit disposed over the second region;

one or more electrically inactive dummy structures laterally disposed between the NVM or the poly SiON CMOS device and the periphery circuit, wherein a bottom surface of the one or more electrically inactive dummy structures is disposed over a top surface of the semiconductor substrate; and

a shallow trench isolation (STI) region comprising a first upper surface and a second upper surface that is recessed to a depth in comparison with the first upper surface to provide a recessed portion of the STI region, wherein the recessed portion of the STI region is laterally offset from the one or more electrically inactive dummy structures.

2. The IC of claim 1, wherein the one or more electrically inactive dummy structures comprise:

a first dummy structure located at a first location overlying the first region, and laterally disposed between the NVM or poly SiON CMOS device and the boundary region; and

a second dummy structure located at a second location overlying the second region, and laterally disposed between the periphery circuit and the boundary region.

3. The IC of claim 1, wherein the depth ranges between approximately 0 angstroms and approximately 200 angstroms.

4. The IC of claim 2, wherein the first dummy structure has an angled sidewall facing the boundary region, and a substantially vertical sidewall opposing the angled sidewall.

5. The IC of claim 2, wherein the second dummy structure comprises vertical sidewalls on both sides.

6. The IC of claim 2, further comprising:

a second STI region disposed within the semiconductor substrate at a second position that is laterally located between the first dummy structure and the NVM or the poly SiON CMOS device.

7. The IC of claim 2, wherein the first dummy structure comprises a polysilicon gate overlying a SiON dielectric layer and the second dummy structure comprises a high-k metal gate overlying a base dielectric layer.

8. The IC of claim 1, wherein the first upper surface is substantially aligned with an upper surface of the semiconductor substrate;

and

wherein the recessed portion of the STI region has an angled sidewall.

9. The IC of claim 2, wherein the recessed portion of the STI region is arranged between the first dummy structure and the second dummy structure.

10. An integrated circuit (IC) comprising:

a semiconductor substrate comprising an embedded memory region and a periphery region separated by a boundary region;

a non-volatile memory (NVM) or a poly SiON (silicon oxy-nitride) CMOS device disposed over the embedded memory region;

a periphery circuit disposed over the periphery region;

an angled first dummy structure positioned at a first end of the embedded memory region; and

a second dummy structure positioned at a second end of the periphery region.

11. The IC of claim 10, wherein the semiconductor substrate comprises a top surface within the boundary region that is recessed to a depth in comparison with top surfaces of the embedded memory and periphery regions.

12. The IC of claim 11, further comprising a high voltage (HV) HKMG transistor disposed over a HV dielectric layer on the periphery region.

13. The IC of claim 12, wherein the HV HKMG transistor comprises:

a high-k dielectric layer disposed over the HV dielectric layer;

an etch-stop layer disposed over the high-k dielectric layer; and

a metal gate layer disposed over the etch-stop layer.

14. The IC of claim 13, wherein the embedded memory region comprises a pair of split-gate flash memory cells, respectively comprising:

a select gate (SG);

a memory gate (MG);

a charge-trapping layer arranged between neighboring sidewalls of the MG and the SG, wherein the charge-trapping layer extends under the MG; and

a sidewall spacer abutting an outer sidewall of the MG.

15. The IC of claim 14, wherein the pair of split-gate flash memory cells resides over a first dielectric layer and a second dielectric layer is laterally arranged between the pair of split-gate flash memory cells.

16. The IC of claim 15, further comprising:

a plurality of source/drain regions disposed within the semiconductor substrate;

a silicide layer located over the source/drain regions;

a contact etch-stop layer (CESL) disposed over the silicide layer; and

metal contacts extending from the silicide layer to an overlying metal interconnect layer.

17. The IC of claim 16, wherein:

the semiconductor substrate comprises silicon;

the SG and the MG comprise polysilicon or metal;

the first dielectric layer comprises SiON (silicon oxy-nitride), SiO₂ (silicon dioxide), or SiN (silicon nitride);

the second dielectric layer comprises SiON, SiO2, or SiN;

the sidewall spacer comprises SiON, SiO2, or SiN; and

the high-k dielectric layer comprises HfO (hafnium oxide), HfSiO (hafnium silicon oxide), HfAlO (hafnium aluminum oxide), or HfTaO (hafnium tantalum oxide).

18. A method of forming an integrated circuit (IC), comprising:

providing a semiconductor substrate comprising a first region and a second region laterally separated from the first region by a boundary region;

forming a non-volatile memory (NVM) device over the first region;

forming one or more HKMG (high-k metal gate) CMOS devices over the second region; and

forming a first dummy structure at a position laterally disposed between the NVM device and the one or more HKMG CMOS devices;

forming a second dummy structure at a position laterally disposed between the first dummy structure and the HKMG CMOS devices.

19. The method of claim 18, wherein the first dummy structure has an angled sidewall facing the boundary region, and a substantially vertical sidewall opposing the angled sidewall.