Wireless processor, wireless memory, information system, and semiconductor device

• US 9,425,215 B2
• Filed: 07/17/2015
• Issued: 08/23/2016
• Est. Priority Date: 07/14/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Kato, Kiyoshi, Koyama, Jun, Shionoiri, Yutaka
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US14/801,936
• Publication Number:
  US 20150325599A1
• Time in Patent Office: 403 Days
• Field of Search: 257/414, 235/454
• US Class Current: 1/1
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

Claims

1. A wireless processor comprising:

an element forming region comprising a transistor, the transistor comprising a semiconductor film with a thickness of 10 to 200 nm; and

an antenna,

wherein the transistor is fixed on a flexible substrate; and

wherein the transistor comprises;

a bottom electrode;

a first insulating film over the bottom electrode;

the semiconductor film over the first insulating film, the semiconductor film comprising a channel formation region;

a second insulating film over the semiconductor film; and

a gate electrode over the second insulating film.

2. The wireless processor according to claim 1, wherein the semiconductor film comprises an amorphous semiconductor or a crystalline semiconductor.

3. The wireless processor according to claim 1,

wherein the semiconductor film comprises an impurity region, and

wherein the impurity region and the gate electrode do not overlap each other.

4. The wireless processor according to claim 1, further comprising a third insulating film being in contact with the second insulating film and the gate electrode.

5. The wireless processor according to claim 1, further comprising:

a first wiring being electrically connected to the bottom electrode; and

a second wiring being electrically connected to the gate electrode.

6. The wireless processor according to claim 1, wherein the bottom electrode and the gate electrode are separately controlled.

7. The wireless processor according to claim 1, wherein the bottom electrode is electrically connected to the gate electrode.

8. The wireless processor according to claim 1, wherein a threshold voltage of the transistor is controlled by the bottom electrode.

9. A wireless memory comprising:

an element forming region comprising a transistor, the transistor comprising a semiconductor film with a thickness of 10 to 200 nm; and

an antenna,

wherein the transistor is fixed on a flexible substrate; and

wherein the transistor comprises;

a bottom electrode;

a first insulating film over the bottom electrode;

the semiconductor film over the first insulating film, the semiconductor film comprising a channel formation region;

a second insulating film over the semiconductor film; and

a gate electrode over the second insulating film.

10. The wireless memory according to claim 9, wherein the semiconductor film comprises an amorphous semiconductor or a crystalline semiconductor.

11. The wireless memory according to claim 9,

wherein the semiconductor film comprises an impurity region, and

wherein the impurity region and the gate electrode do not overlap each other.

12. The wireless memory according to claim 9, further comprising a third insulating film being in contact with the second insulating film and the gate electrode.

13. The wireless memory according to claim 9, further comprising:

a first wiring being electrically connected to the bottom electrode; and

a second wiring being electrically connected to the gate electrode.

14. The wireless memory according to claim 9, wherein the bottom electrode and the gate electrode are separately controlled.

15. The wireless memory according to claim 9, wherein the bottom electrode is electrically connected to the gate electrode.

16. The wireless memory according to claim 9, wherein a threshold voltage of the transistor is controlled by the bottom electrode.