Semiconductor device with low-K spacers

• US 9,425,280 B2
• Filed: 05/13/2015
• Issued: 08/23/2016
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Cai, Xiuyu, Xie, Ruilong, Zhang, Xunyuan
• Primary Examiner(s): Henry, Caleb
• Assistant Examiner(s): AMER, MOUNIR S
• Application Number:
  US14/711,196
• Publication Number:
  US 20150255561A1
• Time in Patent Office: 468 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

Claims

1. A device, comprising:

a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;

a first layer of insulating material positioned above and covering at least a portion of said active region;

a second layer of insulating material positioned above and covering at least a portion of said first layer of insulating material;

a third layer of insulating material positioned above and covering at least a portion of said second layer of insulating material; and

a low-k sidewall spacer positioned adjacent each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer contacts each of said first, second, and third layers of insulating material, wherein a portion of said low-k sidewall spacer extends into a recess that is positioned between said third layer of insulating material and said active region, said portion of said low-k sidewall spacer contacting a sidewall portion of said second layer of insulating material.

2. The device of claim 1, wherein said low-k sidewall spacer is comprised of a material having a k value of less than 7.

3. The device of claim 1, wherein said low-k sidewall spacer is positioned adjacent and contacts each of said vertically oriented upstanding portions of said gate insulation layer.

4. The device of claim 1, further comprising a void formed in said low-k sidewall spacer.

5. The device of claim 1, wherein said gate insulation layer is comprised of a high-k insulating material and said gate electrode is comprised of at least one layer of metal.

6. The device of claim 1, further comprising a fourth layer of insulating material positioned above and covering at least a portion of said third layer of insulating material, wherein said low-k sidewall spacer contacts said fourth layer of insulating material.

7. The device of claim 6, further comprising a gate cap layer positioned above and covering an upper surface of said gate structure, wherein an upper surface of said gate cap layer is substantially coplanar with an upper surface of said fourth layer of insulating material.

8. The device of claim 6, wherein said low-k sidewall spacer contacts an upper surface of said first layer of insulating material and a sidewall surface of each of said second, third, and fourth layers of insulating material.

9. A device, comprising:

a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;

a first layer of insulating material positioned above a portion of said active region;

a second layer of insulating material positioned above a portion of said active region;

a third layer of insulating material positioned above said second layer of insulating material; and

a low-k sidewall spacer that is positioned adjacent to and contacts each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer is positioned above and covers a portion of an upper surface of said first layer of insulating material and wherein said low-k sidewall spacer is positioned laterally adjacent to and covers a portion of a sidewall surface of each of said second and third layers of insulating material.

10. The device of claim 9, further comprising a void formed in said low-k sidewall spacer.

11. The device of claim 9, wherein a portion of said low-k sidewall spacer extends into a recess that is positioned below said third layer of insulating material, above said active region, and between said second layer of insulating material and said gate electrode structure.

12. The device of claim 11, wherein said gate insulation layer is comprised of a high-k insulating material and said gate electrode is comprised of at least one layer of metal.

13. The device of claim 9, wherein said low-k sidewall spacer is comprised of a material having a k value of less than 7.

14. A device, comprising:

a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;

a low-k sidewall spacer that is positioned adjacent to and contacts each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer is comprised of a material having a k value of less than 7;

a void positioned within said low-k sidewall spacer;

a first layer of insulating material positioned above said semiconducting substrate and covering at least a portion of an upper surface of said active region;

a second layer of insulating material positioned above said semiconducting substrate and covering at least a portion of an upper surface of said first layer of insulating material;

a third layer of insulating material positioned above and covering at least a portion of an upper surface of said second layer of insulating material; and

a fourth layer of insulating material positioned above and covering at least a portion of an upper surface of said third layer of insulating material, wherein said low-k sidewall spacer contacts an upper surface of said first layer of insulating material and a sidewall surface of each of said second, third, and fourth layers of insulating material.

15. The device of claim 14, further comprising raised source/drain regions, wherein at least a portion of said second layer of insulating material is positioned above and covers at least a portion of said raised source drain regions.

16. The device of claim 15, wherein a portion of said low-k sidewall spacer is positioned in a recess that is defined by an upper surface of said raised source/drain regions, said sidewall surface of said second layer of insulating material, and a lower surface of said third layer of insulating material.

17. The device of claim 16, further comprising a gate cap layer positioned above and covering an upper surface of said gate structure, wherein an upper surface of said gate cap layer is substantially coplanar with an upper surface of said fourth layer of insulating material.