Source/drain contacts for non-planar transistors

• US 9,425,316 B2
• Filed: 12/17/2015
• Issued: 08/23/2016
• Est. Priority Date: 10/01/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pradhan, Sameer S., Joshi, Subhash M., Chun, Jin-Sung
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US14/972,793
• Publication Number:
  US 20160111532A1
• Time in Patent Office: 250 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02 Manufacture or treatment of semiconductor devices or of parts thereof
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/32053 of metal-silicide layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Claims

1. An apparatus, comprising:

a fin comprising silicon;

a non-planar gate electrode over at least a portion of the fin;

a first spacer on a first side of the gate electrode;

a second spacer on a second side of the gate electrode;

a first dielectric material, the first spacer being between the gate electrode and at least a portion of the first dielectric material;

a cap dielectric layer above the gate electrode, at least a portion of the first dielectric material being below the cap dielectric layer;

a second dielectric layer above the cap dielectric layer;

a source region at least partially in the fin, the source region comprising silicon and at least one other element;

a silicide region on the source region, the silicide region comprising silicon and titanium and being at least substantially free from nickel;

a source contact that is in contact with at least a portion of the second dielectric layer, at least a portion of the cap dielectric layer, and at least a portion of the first dielectric material, the source contact comprising;

an interface layer on a bottom and sides of the contact, the contact interface layer comprising titanium and nitrogen; and

a contact fill material, the contact fill material comprising tungsten, the interface layer being between at least a portion of the contact fill material and the silicide region at the bottom of the contact, and the interface layer being between at least a portion of the fill material and at least a portion of the first dielectric material at the sides of the contact, and the interface layer further being between at least a portion of the contact fill material and at least a portion of the second dielectric material at the sides of the contact; and

wherein, in at least one cross section through the fin, all of the silicide region is under the source contact.

2. The apparatus of claim 1, wherein the source region is at least partially in a recess in the fin.

3. The apparatus of claim 1, wherein the source region comprises a doped region of the fin.

4. The apparatus of claim 1, wherein the capping layer comprises silicon and nitrogen.

5. The apparatus of claim 1, wherein the first and second spacers comprise silicon and nitrogen.

6. The apparatus of claim 1, wherein substantially none of the capping layer is above the first dielectric material.

7. The apparatus of claim 1, wherein a first side of the source contact that is closest to the gate electrode is in contact with the capping layer and a second side of the source contact opposite the first side is not in contact with the capping layer.

8. The apparatus of claim 1, wherein the second dielectric material comprises silicon and oxygen.

9. The apparatus of claim 1, wherein the silicide region does not extend beyond the sides of the source contact.

10. An apparatus, comprising:

a fin comprising silicon;

a non-planar gate electrode over at least a portion of the fin;

a first spacer on a first side of the gate electrode;

a second spacer on a second side of the gate electrode;

a first dielectric material, the first spacer being between the gate electrode and at least a portion of the first dielectric material;

a cap dielectric layer above the gate electrode, at least a portion of the first dielectric material being below the cap dielectric layer;

a second dielectric layer above the cap dielectric layer;

a source region at least partially in the fin, the source region comprising silicon and at least one other element;

a silicide region on the source region, the silicide region comprising silicon and titanium and being at least substantially free from nickel;

a source contact that extends through at least a portion of the second dielectric layer, at least a portion of the first dielectric material, and is in contact with at least a portion of the cap dielectric layer, and at least a portion of the first dielectric material, the source contact including an interface layer comprising titanium and nitrogen and a fill material comprising tungsten interior to the interface layer; and

wherein, in at least one cross section through the fin, substantially all of the silicide region is under the source contact.

11. The apparatus of claim 10, wherein the source region is at least partially in a recess in the fin.

12. The apparatus of claim 10, wherein the source region comprises a doped region of the fin.

13. The apparatus of claim 10, wherein the capping layer comprises silicon and nitrogen.

14. The apparatus of claim 10, wherein the first and second spacers comprise silicon and nitrogen.

15. The apparatus of claim 10, wherein substantially none of the capping layer is above the first dielectric material.

16. The apparatus of claim 10, wherein a first side of the source contact that is closest to the gate electrode is in contact with the capping layer and a second side of the source contact opposite the first side is not in contact with the capping layer.

17. The apparatus of claim 10, wherein the second dielectric material comprises silicon and oxygen.

18. The apparatus of claim 10, wherein the silicide region does not extend beyond the sides of the source contact.

19. The apparatus of claim 10, further comprising:

a drain region at least partially in the fin, the drain region comprising silicon and at least one other element;

a second silicide region on the drain region, the second silicide region comprising silicon and titanium and being at least substantially free from nickel;

a drain contact that extends through at least a portion of the second dielectric layer, at least a portion of the first dielectric material, and is in contact with at least a portion of the cap dielectric layer, and at least a portion of the first dielectric material, the drain contact including an interface layer comprising titanium and nitrogen and a fill material comprising tungsten interior to the interface layer; and

wherein, in at least one cross section through the fin, substantially all of the second silicide region is under the drain contact.