Through silicon via including multi-material fill

• US 9,425,328 B2
• Filed: 09/11/2013
• Issued: 08/23/2016
• Est. Priority Date: 09/12/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marx, David Lambe, Bircumshaw, Brian, Bryzek, Janusz
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US14/023,869
• Publication Number:
  US 20140070339A1
• Time in Patent Office: 1,077 Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0242 Gyroscopes
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0136 Comb structures
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81B 7/0041 maintaining a controlled atmosphere with techniques not provided for in B81B7/0038
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An apparatus includes a substrate having at least one via disposed in the substrate, wherein the substrate includes a trench having a substantially trapezoidal cross-section, the trench extending through the substrate between a lower surface of the substrate and an upper surface of the substrate, wherein the top of the trench opens to a top opening, and the bottom of the trench opens to a bottom opening, the top opening being larger than the bottom opening. The apparatus can include a mouth surrounding the top opening and extending between the upper surface and the top opening, wherein a mouth opening in the upper surface is larger than the top opening of the trench, wherein the via includes a dielectric layer disposed on an inside surface of a trench. The apparatus includes and a fill disposed in the trench, with the dielectric layer sandwiched between the fill and the substrate.

Claims

1. An apparatus comprising:

a substrate including at least one via disposed in the substrate, wherein the substrate comprises;

a trench having a substantially trapezoidal cross-section, the trench extending through the substrate between a lower surface of the substrate and an upper surface of the substrate, wherein the top of the trench opens to a top opening, and the bottom of the trench opens to a bottom opening, the top opening being larger than the bottom opening; and

a mouth surrounding the top opening and extending between the upper surface and the top opening, wherein a mouth opening in the upper surface is larger than the top opening of the trench,

a second substrate bonded to the substrate;

wherein the via comprises;

a dielectric layer disposed on an inside surface of a trench; and

a fill disposed in the trench, with the dielectric layer sandwiched between the fill and the substrate,

wherein the trench defines a circuit in the substrate, with an inner portion of the substrate being in the circuit, and an outer portion surrounding the circuit,

wherein the second substrate includes a sense capacitor, wherein one electrode is formed by a device substrate connected through a conductive substrate bond to a first contact coupled to the inner portion and another electrode is formed by a second contact coupled to the outer portion.

2. The apparatus of claim 1, wherein the substrate is formed of single crystal silicon.

3. The apparatus of claim 1, wherein the fill and the dielectric are sealed to the substrate hermetically.

4. The apparatus of claim 1, wherein the trench tapers narrower in cross-section from the top opening to the bottom opening.

5. The apparatus of claim 1, wherein the via is substantially void free.

6. The apparatus of claim 1, wherein the fill includes at least one of polysilicon or a combination of semiconductor and dielectric.

7. The apparatus of claim 1, wherein the dielectric is recessed below substrate surface.

8. The apparatus of claim 1, wherein the fill is recessed below the upper surface.

9. The apparatus of claim 1, wherein the sense capacitor includes an out-of-plane sense capacitor.

10. The apparatus of claim 1, wherein the sense capacitor includes an in-plane sense capacitor.

11. The apparatus of claim 10, wherein the in-plane sense capacitor includes a comb including interdigitated fingers.

12. The apparatus of claim 10, wherein the second substrate includes an out-of-plane sense capacitor.

13. The apparatus of claim 1, comprising a third substrate including at least one via disposed in the third substrate, wherein the third substrate comprises:

a trench having a substantially trapezoidal cross-section, the trench extending through the third substrate between a lower surface of the third substrate and an upper surface of the third substrate, wherein the top of the trench opens to a top opening, and the bottom of the trench opens to a bottom opening, the top opening being larger than the bottom opening; and

a mouth surrounding the top opening and extending between the upper surface and the top opening, wherein a mouth opening in the upper surface is larger than the top opening of the trench, and

wherein the via comprises;

a dielectric layer disposed on an inside surface of a trench; and

a fill disposed in the trench, with the dielectric layer sandwiched between the fill and the third substrate.

14. The apparatus of claim 1, comprising a cap bonded to an opposite side of second substrate bonded to the second substrate with at least one support structure that supports the cap.

15. The apparatus of claim 14, wherein the support structure is one of a plurality of support structures and includes a pillar.

16. The apparatus of claim 15, wherein the plurality of support structures form cavities, each sealable under different pressure and/or different levels of hermiticity, with each cavity covering a device portion of the second substrate.

17. The apparatus of claim 16, wherein a first cavity covers an acceleration sensor, a second cavity covers an ambient pressure and a third cavity covers a gyroscope.

18. The apparatus of claim 1, wherein the inner portion is dielectrically isolated from the outer portion.

19. The apparatus of claim 1, wherein each of the top opening and the bottom opening are less than 30 μ

m across, and distance between them is from 5 μ

m to 500 μ

m.

20. The apparatus of claim 1, wherein the upper surface is part of a cavity selectively etched into a top of the semiconductor substrate.

21. The apparatus of claim 20, wherein the top opening and the mouth are disposed within the cavity.

22. The apparatus of claim 20, wherein the cavity includes a cavity edge, and wherein the cavity edge to via spacing is no less than 5 μ

m.