Current sensors and methods of improving accuracy thereof

• US 9,425,788 B1
• Filed: 03/18/2015
• Issued: 08/23/2016
• Est. Priority Date: 03/18/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Roberto, Quaglino, Jin, Minghao, Blank, Oliver
• Primary Examiner(s): LUU, AN T
• Application Number:
  US14/661,960
• Time in Patent Office: 524 Days
• Field of Search: 327 50- 51, 327 80- 81, 327/306, 327/313, 327323-324, 327327-328, 257/231, 257/234
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H03K 2217/0027 : Measuring means of, e.g. currents through or voltages across the switch

Abstract

A method for operating a circuit includes providing a three terminal main transistor and a four terminal sense transistor having a field plate. The method includes simultaneously applying a gate pulse on a gate terminal of the sense transistor and a gate terminal of the main transistor, and applying a field plate pulse on a field plate of the sense transistor. The field plate pulse is synchronous and in phase with the gate pulse.

Claims

1. A method for operating a circuit comprising:

providing a three terminal main transistor;

providing a four terminal sense transistor comprising a field plate;

simultaneously applying a gate pulse on a gate terminal of the sense transistor and a gate terminal of the main transistor; and

applying a field plate pulse on a field plate of the sense transistor, wherein the field plate pulse is synchronous and in phase with the gate pulse.

2. The method of claim 1, wherein the field plate is capacitively coupled to a drift region of the sense transistor.

3. The method of claim 1, wherein the main transistor and the sense transistor comprise vertical transistors.

4. The method of claim 3, wherein the main transistor and the sense transistor comprise trench gate transistors.

5. The method of claim 1, wherein the main transistor and the sense transistor comprise lateral transistors.

6. The method of claim 5, wherein the lateral transistors comprise transistors disposed in a gallium nitride on silicon substrate.

7. A circuit comprising:

a three terminal power transistor; and

a four terminal sense transistor comprising a field plate, wherein a drain terminal of the four terminal sense transistor is coupled to a drain terminal of the three terminal power transistor, wherein a gate terminal of the four terminal sense transistor is coupled to a gate terminal of the three terminal power transistor, wherein the field plate is capacitively coupled to a drift region of the four terminal sense transistor, and wherein the field plate is not coupled to the other terminals of the four terminal sense transistor.

8. The circuit of claim 7, wherein the field plate is configured to adjust a resistance of the drift region of the four terminal sense transistor.

9. The circuit of claim 7, wherein the three terminal power transistor and the four terminal sense transistor comprise vertical trench gate transistors.

10. The circuit of claim 7, wherein the three terminal power transistor and the four terminal sense transistor comprise lateral transistors.

11. The circuit of claim 10, wherein the lateral transistors comprise transistors disposed in a gallium nitride on silicon substrate.

12. The circuit of claim 10, wherein the lateral transistors comprise drain extended MOS transistors, Lateral Double-Diffused MOS transistors, Double-Diffused Drain MOS transistors.

13. A method for performing an initialization of a circuit, the method comprising:

providing a three terminal main transistor;

providing a four terminal sense transistor comprising a field plate;

applying a gate pulse on a gate terminal of the sense transistor and a gate terminal of the main transistor;

measuring a ratio of a current through the main transistor and a current through the sense transistor; and

determining a field plate bias needed to be applied at the field plate to maintain the ratio of the current through the main transistor to the current through the sense transistor with a target ratio.

14. The method of claim 13, wherein the target ratio is within −

2% to +2%.

15. The method of claim 13, further comprising:

determining a reference voltage for the field plate bias to be applied during normal operation of the circuit based on the determined field plate bias; and

adjusting the reference voltage of the circuit.

16. The method of claim 15, further comprising:

applying an operational gate pulse on a gate terminal of the sense transistor and a gate terminal of the main transistor; and

applying a field plate pulse on a field plate of the sense transistor, wherein the field plate pulse is synchronous and in phase with the operational gate pulse.

17. A semiconductor device comprising:

a three terminal main transistor disposed in a substrate and comprising a source contact, a drain contact, and a gate contact, the main transistor comprising

a first plurality of trenches disposed at a front side in a first region of the substrate, wherein each of the first plurality of trenches comprises a gate line coupled to the gate contact, and wherein portions of each of the first plurality of trenches not filled with material of the gate line comprise a dielectric material; and

a four terminal sense transistor disposed in the substrate and comprising a source contact, a drain contact, a gate contact, and a field plate contact, the sense transistor comprising

a second plurality of trenches disposed at the front side in a second region of the substrate, wherein each of the second plurality of trenches comprises a gate line coupled to the gate contact, and wherein each of the second plurality of trenches comprises a field plate line coupled to the field plate contact, wherein the total number of trenches in the second plurality of trenches is different from the total number of trenches in the first plurality of trenches.

18. The device of claim 17, further comprising:

first source regions disposed between adjacent first plurality of trenches; and

second source regions disposed between adjacent second plurality of trenches.

19. The device of claim 18, further comprising:

a common drain disposed at a back side of the substrate.

20. The device of claim 17, wherein the field plate line is capacitively coupled to a drift region of the sense transistor.

21. The device of claim 17, wherein the gate contact of the sense transistor is coupled to the gate contact of the main transistor.