Target mapping and implementation of abstract device model

• US 9,426,033 B2
• Filed: 10/26/2015
• Issued: 08/23/2016
• Est. Priority Date: 02/25/2013
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Cohn, Daniel Todd, Crabbe, Edward, Yadav, Navindra
• Primary Examiner(s): Russell, Wanda Z
• Application Number:
  US14/922,964
• Publication Number:
  US 20160099839A1
• Time in Patent Office: 302 Days
• Field of Search: 370/360, 370/386, 709/223
• US Class Current: 1/1
• CPC Class Codes: H04L 41/0803 Configuration setting
• CPC Class Codes: H04L 41/0806 for initial configuration or provisioning, e.g. plug-and-play
• CPC Class Codes: H04L 41/0869 Validating the configuration within one network element
• CPC Class Codes: H04L 41/145 involving simulating, designing, planning or modelling of a network
• CPC Class Codes: H04L 41/342 between virtual entities, e.g. orchestrators, SDN or NFV entities

Abstract

A Hardware Abstraction Layer (HAL) for a target computing device that is equipped with an Application Specific Integrated Circuit (ASIC) or other hardware element that provides forwarding and/or switching capability is used to analyze an abstract candidate device model. The abstract candidate device model is received from a controller and specifies intended forwarding behavior for the target device. The HAL analyzes the abstract candidate device model based on its knowledge of the architecture of the ASIC or other hardware element providing forwarding or switching capability to the target device. If the behavior is supported by the target device'"'"'s architecture, the model may be implemented in a specific manner supported by that architecture and used to control forwarding behavior on the target device.

Claims

1. A method comprising:

mapping, using a Hardware Abstraction Layer (HAL) for a target computing device, to an existing architecture of the target computing device, an abstract candidate device model describing intended packet handling behaviors for the target computing device;

identifying supported behavior by determining, using the HAL, which of the intended packet handling behaviors is supported by the target computing device; and

implementing the identified supported behavior on the target computing device.

2. The method of claim 1, wherein the target computing device is a switch.

3. The method of claim 1, wherein the intended packet handling behaviors include packet forwarding or switching behaviors.

4. The method of claim 1, wherein the intended packet handling behaviors includes mandatory behaviors and non-mandatory behaviors.

5. The method of claim 1, wherein the abstract candidate device model describes a parse tree, one or more abstract tables and corresponding table characteristics, and any lookups or transforms to be performed in a datapath.

6. The method of claim 1, comprising:

identifying a first proposed implementation of the abstract candidate device model, the first proposed implementation omitting an intended behavior;

generating a second proposed implementation of the abstract candidate device model with the omitted intended behavior; and

implementing the second proposed implementation.

7. The method of claim 1, further comprising generating a modified abstract candidate device model based on the abstract candidate device model and the identified supported behavior.

8. The method of claim 7, wherein implementing the identified supported behavior on the target computing device comprises implementing the modified abstract candidate device model on the target computing device.

9. The method of claim 7, wherein implementing the identified supported behavior on the target computing device further comprises transmitting the modified abstract candidate device model to the target computing device.

10. The method of claim 1, comprising generating the abstract candidate device model.

11. A system comprising:

a target computing device; and

a hardware controller comprising a processor configured for data communication with the target computing device, wherein the hardware controller is configured to;

map, using a Hardware Abstraction Layer (HAL) for the target computing device, to an existing architecture of the target computing device, an abstract candidate device model describing intended packet handling behaviors for the target computing device;

identify supported behavior by determining, using the HAL, which of the intended packet handling behaviors is supported by the target computing device; and

implement the identified supported behavior on the target computing device.

12. The system of claim 11, wherein the target computing device is a switch and the intended packet handling behaviors include packet forwarding or switching behaviors.

13. The system of claim 11, wherein the intended packet handling behaviors includes mandatory behaviors and non-mandatory behaviors.

14. The system of claim 11, wherein the abstract candidate device model describes a parse tree, one or more abstract tables and corresponding table characteristics, and any lookups or transforms to be performed in a datapath.

15. The system of claim 11, wherein the target computing device is configured to implement the identified supported behavior using at least one of:

metering, packet fragmentation, packet reassembly, header insertion or removal, network address translation (NAT), and cryptography.

16. The system of claim 11, wherein the hardware controller is configured to generate a modified abstract candidate device model based on the abstract candidate device model and the identified supported behavior.

17. The system of claim 16, wherein the hardware controller is configured to transmit the modified abstract candidate device model to the target computing device.

18. The system of claim 11, wherein the hardware controller is configured to generate the abstract candidate device model.

19. The system of claim 11, wherein the existing architecture of the target computing device includes at least one of:

an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), an Application Specific Instruction Set Processor (ASIP), a Complex Programmable Logic Device (CPLD), a Graphics Processing Unit (GPU), a computing processor, or a microprocessor.

20. A non-transitory computer-readable medium storing computer instructions that, when executed by a computing processor, cause the computing processor to:

map, using a Hardware Abstraction Layer (HAL) for a target computing device, to an existing architecture of the target computing device, an abstract candidate device model describing intended packet handling behaviors for the target computing device;

identify supported behavior by determining, using the HAL, which of the intended packet handling behaviors is supported by the target computing device; and

implement the identified supported behavior on the target computing device.