Test method and test arrangement

• US 9,429,616 B2
• Filed: 06/30/2015
• Issued: 08/30/2016
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Hirler, Franz, Nelle, Peter
• Primary Examiner(s): Hollington, Jermele M
• Application Number:
  US14/754,738
• Publication Number:
  US 20150346270A1
• Time in Patent Office: 427 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

Claims

1. A test method, comprising:

providing a workpiece comprising a transistor to be tested, the transistor comprising a plurality of cells electrically connected in parallel, each of the plurality of cells comprising at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode is separately controllable from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and

applying a plurality of test potentials to at least one of the at least one additional electrodes of the plurality of cells to detect defective cells among the plurality of cells

wherein respectively for each of the plurality of cells, a potential of the at least one additional electrode is electrically insulated from potentials of each of the at least one first terminal electrode region, the at least one second terminal electrode region, and the at least one gate electrode,

wherein the first terminal electrode region is a source region and the second terminal electrode region is a drain region or the first terminal electrode region is a drain region and the second terminal electrode region is a source region.

2. The method of claim 1, wherein applying the plurality of test potentials comprises applying each of the plurality of test potentials commonly to a plurality of the at least one additional electrodes of the plurality of cells.

3. The method of claim 1,

wherein applying the plurality of test potentials comprises applying a plurality of different bias potentials,

wherein the method further comprises measuring a breakdown voltage of the transistor for each of the bias potentials.

4. The method of claim 1,

wherein each of the at least one additional electrodes of the plurality of cells is insulated by an insulating layer disposed in the respective trench,

wherein the method further comprises:

measuring a tunnel current through the insulating layer for each of the plurality of test potentials.

5. The method of claim 1,

wherein the workpiece further comprises a plurality of pads including at least a first pad coupled to the at least one first terminal electrode region, a second pad coupled to the at least one second terminal electrode region, a third pad coupled to the at least one gate electrode and a fourth pad coupled to the at least one additional electrode of each cell,

wherein the fourth pad coupled to the at least one additional electrode is electrically insulated from the first to third pads.

6. The method of claim 5,

wherein applying the plurality of test potentials is carried out in a front end processing stage of the workpiece;

and

the method further comprising;

electrically connecting the fourth pad to at least one of the first to third pads in a back end processing stage of the workpiece.

7. The method of claim 1,

wherein applying the plurality of test potentials comprises carrying out an avalanche test.

8. The method of claim 7,

wherein the avalanche test comprises applying one or more avalanche pulses to the transistor.

9. The method of claim 1,

wherein applying the plurality of test potentials comprises subjecting the transistor to at least one of a defect density scan and a reliability scan.

10. The method of claim 1, further comprising:

analyzing test results obtained by applying the plurality test potentials by means of dynamical part average testing (PAT).

11. The method of claim 1, wherein respectively for one or more of the plurality of cells, the corresponding at least one gate electrode is at least partially in the at least one trench.

12. The method of claim 1, wherein respectively for one or more of the plurality of cells, the corresponding at least one additional electrode is configured as a shield electrode.

13. The method of claim 1, wherein applying the plurality of test potentials comprises forcing a predeterminable electrical current through the transistor.

14. The method of claim 1, wherein respectively for one or more of the plurality of cells, at least one of the corresponding at least one gate electrode and the corresponding at least one additional electrode comprises polysilicon.

15. A test method, comprising:

providing a semiconductor device to be tested, the semiconductor device being a diode comprising at least one device cell, the at least one device cell comprising;

at least one trench,

at least one first terminal electrode region having a first conductivity type,

at least one second terminal electrode region having a second conductivity type that is opposite the first conductivity type,

a body region formed between the first terminal electrode region and the second terminal electrode region, wherein the body region has the same conductivity type as the first terminal electrode region, and

at least one electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one electrode is separately controllable from electrical potentials of the at least one first terminal electrode region and the at least one second terminal electrode region; and

applying at least one electrical test potential to at least the at least one electrode to detect defects in the at least one device cell,

wherein respectively for each of the at least one device cell, a potential of the at least one electrode is electrically insulated from potentials of each of the at least one first terminal electrode region, and the at least one second terminal electrode region.

16. The test method of claim 15, wherein the at least one device cell comprises only one electrode disposed in the trench.

17. The test method of claim 15, wherein the first terminal electrode region has a higher doping concentration than the body region.

18. The test method of claim 15, wherein the at least one device cell comprises a PN junction formed by the body region and the second terminal electrode region.

19. The test method of claim 15, wherein the first terminal electrode region is an anode region and the second terminal electrode region is a cathode region or the first terminal electrode region is a cathode region and the second terminal electrode region is an anode region.

20. The method of claim 15,

wherein applying the plurality of test potentials comprises carrying out an avalanche test.

21. The method of claim 20,

wherein the avalanche test comprises applying one or more avalanche pulses to the transistor.

22. The method of claim 15,

wherein applying the plurality of test potentials comprises subjecting the transistor to at least one of a defect density scan and a reliability scan.

23. The method of claim 15, further comprising:

analyzing test results obtained by applying the plurality test potentials by means of dynamical part average testing (PAT).