Intelligent voltage regulator

• US 9,429,964 B2
• Filed: 06/20/2014
• Issued: 08/30/2016
• Est. Priority Date: 03/12/2007
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Inventors: Wright, David G.
• Primary Examiner(s): Hernandez, William
• Application Number:
  US14/310,530
• Publication Number:
  US 20140300337A1
• Time in Patent Office: 802 Days
• Field of Search: 323/234, 323/265, 323/282, 323/283, 323/284, 323/299, 327/306, 327/331, 327/332, 327/530, 327/538, 327/540, 327/541, 327/543
• US Class Current: 1/1
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03L 5/02 of power
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.

Claims

1. A device comprising:

a voltage generator including;

a first resistor ladder configured to receive an input voltage and to generate a plurality of voltage signals based, at least in part, on the input voltage;

a first multiplexer in communication with the first resistor ladder and configured to generate a selected voltage signal from the plurality of voltage signals;

a second resistor ladder configured to generate a plurality of reset voltage signals; and

a second multiplexer in communication with the second resistor ladder and configured to generate a threshold reset reference voltage from the plurality of reset voltage signals; and

a processing device coupled to the voltage generator and configured to receive and execute a programming instructions, wherein the processing device is further configured to, based, at least in part, on execution of the programming instructions;

generate a selection signal and a threshold reset selection signal;

provide the selection signal to the first multiplexer; and

provide the threshold reset selection signal to the second multiplexer;

wherein the voltage generator is further configured to generate;

a selected voltage signal from the plurality of voltage signals in response to the selection signal provided to the first multiplexer to generate an output voltage from the input voltage using the selected voltage signal, wherein the output voltage includes a magnitude corresponding to the selected voltage signal; and

the threshold reset reference voltage from the plurality of reset voltage signals in response to the threshold reset selection signal provided to the second multiplexer and to generate a reset signal based on the threshold reset reference voltage.

2. The device of claim 1, further comprising a memory device coupled to the processing device, wherein the memory device is configured to store the programming instructions, and wherein the processing device is configured to receive the programming instructions from the memory device.

3. The device of claim 1, wherein the processing device is configured to receive the programming instructions from a programming interface.

4. The device of claim 1, wherein the voltage generator comprises a follower circuit configured to receive the input voltage and to output the output voltage.

5. The device of claim 1, wherein the processing device comprises one of a central processing unit or a microprocessor.

6. A method comprising:

receiving an input voltage at a voltage generator and generating, at a first resistor ladder, a plurality of voltage signals based, at least in part, on the input voltage;

receiving and executing, at a processing device, a first programming instruction to generate a selection signal;

generating, at a first multiplexer in communication with the first resistor ladder, a selected voltage signal from the plurality of voltage signals in response to providing the selection signal to the first multiplexer;

generating an output voltage from the input voltage using the selected voltage signal, wherein the output voltage includes a magnitude corresponding to the selected voltage signal;

generating, at a second resistor ladder, a plurality of reset voltage signals;

receiving and executing, at the processing device, a second programming instruction to generate a threshold reset selection signal;

generating, at a second multiplexer in communication with the second resistor ladder, a threshold reset reference voltage from the plurality of reset voltage signals in response to providing the threshold reset selection signal to the second multiplexer; and

generating a reset signal based on the threshold reset reference voltage.

7. The method of claim 6, further comprising:

comparing the input voltage with a threshold voltage level; and

disabling the voltage generator from generating the output voltage if the input voltage is a predetermined level relative to the threshold voltage level.

8. The method of claim 6, further comprising storing the first and second programming instructions in a memory device coupled to the processing device, wherein receiving the first and second programming instructions at the processing device comprises receiving the first and second programming instructions from the memory device.

9. The method of claim 6, wherein receiving the first and second programming instructions at the processing device comprises receiving the first and second programming instructions from a programming interface.

10. The method of claim 6, wherein generating an output voltage comprises applying the input voltage to a follower circuit and outputting from the follower circuit the output voltage in response to the selected voltage signal.

11. The method of claim 6, wherein executing the first and second programming instructions at the processing device comprises executing the first and second programming instructions at one of a central processing unit or a microprocessor.

12. A device comprising:

a voltage generator including;

a first resistor ladder configured to receive an input voltage and to generate a plurality of voltage signals based, at least in part, on the input voltage;

a first multiplexer in communication with the first resistor ladder and configured to generate a selected voltage signal from the plurality of voltage signals;

a second resistor ladder configured to generate a plurality of reset voltage signals; and

a second multiplexer in communication with the second resistor ladder and configured to generate a threshold reset reference voltage from the plurality of reset voltage signals;

a processing device coupled to the voltage generator and configured to receive and execute programming instructions, wherein the processing device is further configured to select a selection signal and a threshold reset selection signal based, at least in part, on execution of the programming instructions to provide the selection signal to the first multiplexer and to provide the threshold reset selection signal to the second multiplexer; and

a protection circuit configured to compare the input voltage with a threshold voltage level and to disable the voltage generator from generating the output voltage if the input voltage is a predetermined level relative to the threshold voltage level;

wherein the voltage generator is further configured to generate;

a selected voltage signal from the plurality of voltage signals in response to the selection signal provided to the first multiplexer to generate an output voltage from the input voltage using the selected voltage signal, wherein the output voltage includes a magnitude corresponding to the selected voltage signal; and

the threshold reset reference voltage from the plurality of reset voltage signals in response to the threshold reset selection signal provided to the second multiplexer and to generate a reset signal based on the threshold reset reference voltage.

13. The device of claim 12, further comprising a memory device coupled to the processing device, wherein the memory device is configured to store the programming instructions, and wherein the processing device is configured to receive the programming instructions from the memory device.

14. The device of claim 12, wherein the processing device is configured to receive the programming instructions from a programming interface.

15. The device of claim 12, wherein the voltage generator comprises a follower circuit configured to receive the input voltage and to output the output voltage.

16. The device of claim 12, wherein the processing device comprises one of a central processing unit or a microprocessor.