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CPU current ripple and OCV effect mitigation

  • US 9,429,981 B2
  • Filed: 03/05/2013
  • Issued: 08/30/2016
  • Est. Priority Date: 03/05/2013
  • Status: Active Grant
First Claim
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1. A method of reducing transient variations in power supplied to a processor comprising a plurality of functional processing units, comprising:

  • generating at least first and second clock signals, the second clock signal having the same frequency, but a phase offset, relative to the first clock signal;

    clocking a first functional unit of the processor with the first clock signal;

    clocking a second functional unit of the processor with the second clock signal;

    synchronizing data transfer between the second functional unit and a circuit, other than the first functional unit, that is clocked by the first clock signal by interposing a clock phase synchronization circuit on a data path between the second functional unit and the circuit clocked by the first clock signal; and

    suspending at least one of the first and second clock signals when the associated functional unit of the processor is placed in an inactive state.

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