CPU current ripple and OCV effect mitigation

• US 9,429,981 B2
• Filed: 03/05/2013
• Issued: 08/30/2016
• Est. Priority Date: 03/05/2013
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Inventors: Persson, Hkan
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Derose, Volvick
• Application Number:
  US13/784,909
• Publication Number:
  US 20140258765A1
• Time in Patent Office: 1,274 Days
• Field of Search: 713/501
• US Class Current: 1/1
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads.

Claims

1. A method of reducing transient variations in power supplied to a processor comprising a plurality of functional processing units, comprising:

generating at least first and second clock signals, the second clock signal having the same frequency, but a phase offset, relative to the first clock signal;

clocking a first functional unit of the processor with the first clock signal;

clocking a second functional unit of the processor with the second clock signal;

synchronizing data transfer between the second functional unit and a circuit, other than the first functional unit, that is clocked by the first clock signal by interposing a clock phase synchronization circuit on a data path between the second functional unit and the circuit clocked by the first clock signal; and

suspending at least one of the first and second clock signals when the associated functional unit of the processor is placed in an inactive state.

2. The method of claim 1 wherein the circuit clocked by the first clock signal comprises a memory circuit.

3. The method of claim 1 wherein the phase offset is 180 degrees.

4. The method of claim 3 wherein generating the first and second clock signals having 180 phase offset comprises inverting the first clock signal to generate the second clock signal.

5. The method of claim 3 wherein generating the first and second clock signals having 180 phase offset comprises

generating a source clock signal at twice the desired frequency;

and

dividing the source clock signal by two to generate the first and second clock signals, each of the first and second clock signals separated by one cycle of the source clock frequency.

6. The method of claim 3 further comprising:

clocking a third functional unit of the processor with the first clock signal;

clocking a memory circuit connected to the processor with the second clock signal.

7. The method of claim 6 further comprising:

changing the clocking of one or more functional units between first and second clock signals as one or more functional units changes between active and inactive states.

8. The method of claim 1 further comprising

generating a third clock signals, the third clock signal having a phase offset relative to the first and second clock signals;

and

clocking a third functional unit of the processor with the third clock signal.

9. The method of claim 8 wherein the second clock signal is phase offset from the first clock signal by 120 degrees, and wherein the third clock signal is phase offset from the first clock signal by 240 degrees.

10. The method of claim 9 further comprising changing the phase offset of one or more clock signals.

11. The method of claim 1 wherein the clock phase synchronization circuit comprises one or more stages of pipeline registers.

12. The method of claim 1 further comprising:

generating a plurality of pairs of strobe signals associated with the first and second clock signals, one strobe signal of each pair being asserted to qualify a cycle of one clock signal and the other strobe signal of the pair being asserted to qualify an associated cycle of the other clock signal; and

wherein the clock phase synchronization circuit comprises an On-Chip Variation (OCV) mitigation First In First Out (FIFO) memory circuit including a separate set of read and write pointer registers associated with each pair of strobe signals, the read and write pointers operative to independently index a memory to provide FIFO functionality for each pair of strobe signals.

13. A processor, comprising:

a clock generator circuit operative to generate at least first and second clock signals, the second clock signal having the same frequency, but a phase offset, relative to the first clock signal;

a first functional unit of the processor clocked with the first clock signal;

a second functional unit of the processor clocked with the second clock signal; and

a clock phase synchronization circuit interposed on a data path between the second functional unit and a circuit, other than the first functional unit, that is clocked by the first clock signal and operative to synchronize data transfer between the second functional unit and a circuit clocked by the first clock signal;

wherein the clock generator circuit is further operative to suspend at least one of the first and second clock signals when the associated functional unit of the processor is placed in an inactive state.

14. The processor of claim 13 further comprising a memory circuit, and wherein the circuit clocked by the first clock signal comprises the memory circuit.

15. The processor of claim 13 wherein the phase offset is 180 degrees.

16. The processor of claim 15 further wherein clock generator circuit is operative to generate the second clock signal by inverting the first clock signal.

17. The processor of claim 15 further wherein clock generator circuit is operative to

generate a source clock signal at twice the desired frequency;

and

divide the source clock signal by two to generate the first and second clock signals, each of the first and second clock signals separated by one cycle of the source clock frequency.

18. The processor of claim 15 further comprising:

a third functional unit clocked with the first clock; and

a memory circuit clocked with the second clock.

19. The processor of claim 18 wherein the clock generator circuit is further operative to change the clock signal applied to one or more cores in response to one or more cores changing between active and inactive states.

20. The processor of claim 13

wherein clock generator circuit is further operative to generate a third clock signal, the third clock signal having a phase offset relative to the first and second clock signals;

and

further comprising a third functional unit of the processor clocked with the third clock signal.

21. The processor of claim 20 wherein the second clock signal is phase offset from the first clock signal by 120 degrees, and wherein the third clock signal is phase offset from the first clock signal by 240 degrees.

22. The processor of claim 20 wherein clock generator circuit is further operative to change the phase offset of one or more clock signals.

23. The processor of claim 13 wherein the clock phase synchronization circuit comprises one or more stages of pipeline registers.

24. The processor of claim 13 wherein

the clock generator circuit is further operative to generate a plurality of pairs of strobe signals associated with the first and second clock signals, one strobe signal of each pair being asserted to qualify a cycle of one clock signal and the other strobe signal of the pair being asserted to qualify an associated cycle of the other clock signal;

and

wherein the clock phase synchronization circuit comprises an On-Chip Variation (OCV) mitigation First In First Out (FIFO) memory circuit including a separate set of read and write pointer registers associated with each pair of strobe signals, the read and write pointers operative to independently index a memory to provide FIFO functionality for each pair of strobe signals.

25. An On-Chip Variation (OCV) mitigation First In First Out (FIFO) memory circuit operative to synchronize data between clock phase domains wherein clock signals have the same frequency but different relative phases, and further operative to mitigate the effects of OCV in clock signals, comprising:

in a first clock phase domain,

inputs operative to receive a first clock signal and a plurality of first strobe signals, each first strobe signal operative to qualify a cycle of the first clock signal;

a plurality of data storage registers;

source pointer logic operative to generate write pointers into the data storage registers and to output a plurality of write pointers;

a plurality of write pointer registers, each associated with and qualified by a first strobe signal and operative to receive a write pointer from the source pointer logic and output a write pointer to a second clock phase domain of the OCV mitigation FIFO; and

a read pointer multiplexer operative to receive the plurality of first strobe signals and a plurality of read pointers from the second clock phase domain of the OCV mitigation FIFO and output an active read pointer to the source pointer logic based on the first strobe signals; and

in a second clock phase domain wherein clock signals have the same frequency as, but different relative phases than, clock signals in the first clock phase domain,

inputs operative to receive a second clock signal having a phase offset from the first clock signal and a plurality of second strobe signals, each second strobe signal operative to qualify a cycle of the second clock signal associated with a corresponding cycle of the first clock signal;

target pointer logic operative to generate a plurality of read pointers;

a plurality of read pointer registers, each associated with and qualified by a second strobe signal and operative to receive a read pointer from the target pointer logic and output a read pointer to the first clock phase domain of the OCV mitigation FIFO; and

a write pointer multiplexer operative to receive the plurality of second strobe signals and a plurality of write pointers from the first clock phase domain of the OCV mitigation FIFO and output an active write pointer to the target pointer logic based on the second strobe signals; and

a data multiplexer operative to receive data from the first clock phase domain of the OCV mitigation FIFO and output data based on a read pointer received from the target pointer logic.

26. The OCV mitigation FIFO of claim 25 wherein the read pointer multiplexer, write pointer multiplexer, and data multiplexer are operative to block changes on non-selected inputs from propagating to the respective outputs.