Scalable test platform in a PCI express environment with direct memory access

• US 9,430,349 B2
• Filed: 01/24/2013
• Issued: 08/30/2016
• Est. Priority Date: 01/24/2013
• Status: Active Grant

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: Xcerra Corporation (COHU Incorporated)
• Inventors: Fritzsche, William A., Currin, Jeffery D., Poffenberger, Russell Elliott, Alton, Timothy, Davis, Michael Gordon
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): CONTINO, PAUL F
• Application Number:
  US13/749,308
• Publication Number:
  US 20140208164A1
• Time in Patent Office: 1,314 Days
• Field of Search: 714/27, 714/30, 714/38.14, 714/40
• US Class Current: 1/1
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test

Abstract

A scalable test platform includes a PCIe-based event fabric. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test and generate captured test data. One or more digital signal processing subsystems are coupled to the PCIe-based event fabric and configured to process the captured test data.

Claims

1. A scalable test platform comprising:

one or more PCIe-based event fabrics, wherein the one or more PCIe-based event fabrics include one or more PCIe switches;

one or more instrument subsystems coupled to the one or more PCIe-based event fabrics and configured to interface one or more devices under test, provide an input signal to the one or more devices under test, generate captured test data resulting from the input signal, and store the captured test data within at least one of the one or more instrument subsystems, the one or more instrument subsystems including a first set of one or more direct memory access engines configured to allow the one or more instrument subsystems to read the captured test data from and/or write the captured test data to a remote memory system, wherein the one or more instrument subsystems is one or more instrument cards, and wherein the one or more instrument cards is separate from each of the one or more PCIe switches; and

one or more digital signal processing subsystems externally coupled to the PCIe-based event fabric and configured to process the captured test data, wherein the one or more digital signal processing subsystems includes a second set of one or more direct memory access engines configured to allow the one or more digital signal processing subsystems to obtain the captured test data stored within at least one of the one or more instrument subsystems via a PCIe interface, process the captured test data obtained from within at least one of the one or more instrument subsystems to generate a result set, store the result set, and write the result set directly to the remote memory system accessible by one or more CPU subsystems coupled to the one or more PCIe-based event fabrics.

2. The scalable test platform of claim 1 wherein at least one of the one or more PCIe-based event fabrics include a PCIe backplane.

3. The scalable test platform of claim 1 further comprising:

the one or more CPU subsystems configured to execute an automated test process.

4. The scalable test platform of claim 3 wherein the one or more CPU subsystems includes a stand-alone computer.

5. The scalable test platform of claim 3 wherein the one or more CPU subsystems includes a single-board computer.

6. The scalable test platform of claim 1 wherein the one or more instrument subsystems includes instrument hardware configured to interface with the one or more devices under test.

7. A scalable test platform comprising:

one or more PCIe-based event fabrics, wherein the one or more PCIe-based event fabrics include one or more PCIe switches;

one or more CPU subsystems coupled to the one or more PCIe-based event fabrics and configured to execute an automated test process;

one or more instrument subsystems coupled to the PCIe-based event fabric and configured to interface one or more devices under test, provide an input signal to the one or more devices under test, generate captured test data resulting from the input signal, and store the captured test data within at least one of the one or more instrument subsystems, the one or more instrument subsystems including a first set of one or more direct memory access engines configured to allow the one or more instrument subsystems to read the captured test data from and/or write the captured test data to a remote memory system, wherein the one or more instrument subsystems is one or more instrument cards, and wherein the one or more instrument cards is separate from each of the one or more PCIe switches; and

one or more digital signal processing subsystems externally coupled to the PCIe-based event fabric and configured to process the captured test data, wherein the one or more digital signal processing subsystems includes a second set of one or more direct memory access engines configured to allow the one or more digital signal processing subsystems to obtain the captured test data stored within at least one of the one or more instrument subsystems via a PCIe interface, process the captured test data obtained from within at least one of the one or more instrument subsystems to generate a result set, store the result set, and write the result set directly to the remote memory system accessible by one or more CPU subsystems coupled to the one or more PCIe-based event fabrics.

8. The scalable test platform of claim 7 wherein at least one of the one or more PCIe-based event fabrics include a PCIe backplane.

9. The scalable test platform of claim 7 wherein the one or more CPU subsystems includes a stand-alone computer.

10. The scalable test platform of claim 7 wherein the one or more CPU subsystems includes a single-board computer.

11. A scalable test platform comprising:

one or more PCIe-based event fabrics including a PCIe backplane and one or more PCIe switches;

one or more instrument subsystems coupled to the PCIe-based event fabric and configured to interface one or more devices under test, provide an input signal to the one or more devices under test, generate captured test data resulting from the input signal, and store the captured test data within at least one of the one or more instrument subsystems, the one or more instrument subsystems including a first set of one or more direct memory access engines configured to allow the one or more instrument subsystems to read the captured test data from and/or write the captured test data to one or more digital signal processing subsystems, wherein the one or more instrument subsystems is one or more instrument cards, and wherein the one or more instrument cards is separate from each of the one or more PCIe switches; and

the one or more digital signal processing subsystems externally coupled to the one or more PCIe-based event fabrics and configured to process the captured test data, wherein the one or more digital signal processing subsystems includes a second set of one or more direct memory access engines configured to allow the one or more digital signal processing subsystems to obtain the captured test data stored within at least one of the one or more instrument subsystems via a PCIe interface, process the captured test data obtained from within at least one of the one or more instrument subsystems to generate a result set, store the result set, and write the result set directly to the remote memory system accessible by one or more CPU subsystems coupled to the one or more PCIe-based event fabrics.

12. The scalable test platform of claim 11 further comprising:

the one or more CPU subsystems configured to execute an automated test process.