Apparatus, method and system that stores bios in non-volatile random access memory

• US 9,430,372 B2
• Filed: 09/30/2011
• Issued: 08/30/2016
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nachimuthu, Murugasamy K., Kumar, Mohan
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): WESTBROOK, MICHAEL L
• Application Number:
  US13/997,940
• Publication Number:
  US 20140082262A1
• Time in Patent Office: 1,796 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS.

Claims

1. An apparatus comprising:

a processor that comprises one or more cores;

a non-volatile memory (NVM) coupled to the processor via an I/O interface by the processor, the NVM having stored thereon a compressed Basic Input and Output System (BIOS) image;

a cache within the processor; and

a non-volatile random accessible memory (NVRAM) coupled to the processor and being byte-rewritable and byte-erasable by the processor, the NVRAM having stored thereon an uncompressed BIOS image, which is produced by the processor from the compressed BIOS image during a Pre-Extensible Firmware Interface (PEI) phase of a boot process, wherein execution of the uncompressed BIOS image places the cache in a write-back mode during the PEI phase of the boot process.

2. The apparatus of claim 1, wherein the NVRAM comprises a phase change memory (PCM).

3. The apparatus of claim 1, wherein the NVRAM comprises a phase change memory and switch (PCMS).

4. The apparatus of claim 1, wherein the NVM is coupled to the processor via an I/O subsystem and the NVRAM is coupled to the processor without passing through the I/O subsystem.

5. The apparatus of claim 1, wherein the NVRAM is coupled to the processor via a high speed link that implements a same protocol as inter-processor links.

6. The apparatus of claim 1, wherein the NVM has stored thereon a first portion of code to be copied into the NVRAM as the compressed BIOS image and a second portion of the code to be copied into the NVRAM for uncompressing the compressed BIOS image into the NVRAM.

7. The apparatus of claim 1, wherein the NVRAM comprises a writable area to which debug or error or progress status messages generated during the boot process are written.

8. The apparatus of claim 1, wherein the plurality of BIOS images support multiple platforms or multiple processor families.

9. An apparatus comprising:

a processor that comprises one or more cores;

a non-volatile random accessible memory (NVRAM) coupled to the processor and being byte-rewritable and byte-erasable by the processor, the NVRAM having stored thereon a plurality of BIOS images, one of the BIOS images to be executed by the processor during a Pre-Extensible Firmware Interface (PEI) phase of a boot process; and

a cache within the processor, the cache operated in a write-back mode for execution of the one of the BIOS images during the PEI phase of the boot process.

10. The apparatus of claim 9, wherein the NVRAM comprises a phase change memory (PCM).

11. The apparatus of claim 9, wherein the NVRAM comprises a phase change memory and switch (PCMS).

12. The apparatus of claim 9, wherein the plurality of BIOS images comprise multiple versions of BIOS.

13. The apparatus of claim 9, wherein the NVRAM stores platform firmware.

14. The apparatus of claim 9, wherein the NVRAM comprises a writable area to which debug or error or progress status messages generated during the boot process are written.