Method and system for communicating with non-volatile memory
First Claim
1. A method for managing communication in a flash memory system, the flash memory system comprising a memory controller, a first flash bank and a second flash bank, the first and second flash banks communicatively coupled to the memory controller via a common flash interface, the method comprising the memory controller:
- receiving a first flash command and a second flash command from a host system;
generating from the first flash command, a first command sequence wherein the first command sequence comprises a first atomic portion and a second atomic portion and generating from the second flash command, a second command sequence wherein the second command sequences comprises at least one atomic portion;
attaching a first identifier to each of the first and second portion of the first command sequence identifying the first flash bank, and a second identifier to the at least one portion of the second command sequence identifying the second flash bank;
selecting the first command sequence based on a first criteria and a second criteria, wherein the first criteria is associated with the first command sequence and the second criteria is associated with the second command sequence;
communicating the first portion of the first command sequence to the first flash bank via the common flash interface;
after communicating the first portion, and prior to communicating the second portion of the first command sequence, communicating the at least one portion of the second command sequence to the second flash bank via the common flash interface; and
after communicating the at least one portion of the second command sequence, communicating the second portion of the first command sequence to the first flash bank via the common flash interface.
2 Assignments
0 Petitions
Accused Products
Abstract
Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic. The processor associates each of the plurality of command sequences with a priority, and via the flash interface module, selects one of the plurality of the command sequences based on the priority associated with the one of the plurality of the command sequences and transmits sequentially the first portion of the one of the plurality of the command sequences to either one of the first flash bank or the second flash bank.
27 Citations
19 Claims
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1. A method for managing communication in a flash memory system, the flash memory system comprising a memory controller, a first flash bank and a second flash bank, the first and second flash banks communicatively coupled to the memory controller via a common flash interface, the method comprising the memory controller:
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receiving a first flash command and a second flash command from a host system; generating from the first flash command, a first command sequence wherein the first command sequence comprises a first atomic portion and a second atomic portion and generating from the second flash command, a second command sequence wherein the second command sequences comprises at least one atomic portion; attaching a first identifier to each of the first and second portion of the first command sequence identifying the first flash bank, and a second identifier to the at least one portion of the second command sequence identifying the second flash bank; selecting the first command sequence based on a first criteria and a second criteria, wherein the first criteria is associated with the first command sequence and the second criteria is associated with the second command sequence; communicating the first portion of the first command sequence to the first flash bank via the common flash interface; after communicating the first portion, and prior to communicating the second portion of the first command sequence, communicating the at least one portion of the second command sequence to the second flash bank via the common flash interface; and after communicating the at least one portion of the second command sequence, communicating the second portion of the first command sequence to the first flash bank via the common flash interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for communicating with a first flash bank and a second flash bank via a common flash interface, the method comprising a processor of a memory controller:
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in response to receiving a first flash command from a host, determining that the first flash command is intended to be communicated to the first flash bank; generating a command sequence from the first flash command, wherein the command sequence is associated with a first priority and comprises two portions, each portion comprising a series of commands, wherein the series of commands is atomic; attaching to each portion identification information associated with the first flash bank; communicating a first portion of the command sequence to the first flash bank in response to detecting the first priority; in response to detecting a command in the series of commands in the first portion, generating an status indication, wherein the status indication indicates that the first portion of the command sequence has been communicated to the first flash bank; receiving the indication and determining if another command sequence associated with a second priority and to be communicated to the second flash bank was received; comparing the first priority with the second priority in response to determining that the another command sequence was received; communicating the second portion of the command sequence to the first flash bank in response to the first priority being greater than the second priority; and communicating the another command sequence to the second flash bank in response to the second priority being greater than the first priority. - View Dependent Claims (14, 15)
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13. The method of 12 wherein the first or second priority depends at least in part on nature of the first command sequence or the another command sequence being a read or write of data.
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16. A memory controller for communicating with a first flash bank and a second flash bank, the memory controller comprising:
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a flash interface module configured for communication with the first and second flash banks; and a processor in communication with the flash interface module, the processor configured to; generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system, wherein each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands, wherein some of the plurality of command sequences comprise a first portion and a second portion and each of the first portion and second portion are atomic; attach an identifier to each of the first and second portions identifying either the first or the second flash bank; associate each of the plurality of command sequences with a priority; and via the flash interface module, select one of the plurality of the command sequences based on the priority associated with the one of the plurality of the command sequences and transmit sequentially the first portion of the one of the plurality of the command sequences to either one of the first flash bank or the second flash bank. - View Dependent Claims (17, 18, 19)
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Specification