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Systems, methods, and apparatus to enhance the integrity assessment when using power fingerprinting systems for computer-based systems

  • US 9,430,644 B2
  • Filed: 07/10/2015
  • Issued: 08/30/2016
  • Est. Priority Date: 03/15/2013
  • Status: Active Grant
First Claim
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1. A method, comprising:

  • receiving, at a first module, side-channel information of a first target component of a system, the first module being collocated with the first target component, the side-channel information of the first target component being associated with a plurality of authorized execution statuses of the first target component and an execution status of the first target component;

    obtaining a power fingerprint for the first target component based on the side-channel information for the first target component, the power fingerprint for the first target component representing the plurality of authorized execution statuses of the first target component;

    receiving, at a second module, side-channel information of a second target component of the system, the second module being collocated with the second target component, the side-channel information of the second target component being associated with a plurality of authorized execution statuses of the second target component and an execution status of the second target component;

    obtaining a power fingerprint for the second target component based on the side-channel information for the second target component, the power fingerprint for the second target component representing the plurality of execution statuses of the second target component; and

    sending, from a processor physically separate from the first target component and the second target component, a reporting signal based on at least one of (1) the power fingerprint for the first target component and an execution status of the first target component, or (2) the power fingerprint for the second target component and an execution status of the second target component, the reporting signal associated with at least one of the execution status of the first target component or the execution status of the second target component.

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