Neural network in a memory device
First Claim
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1. A method of operating a memory device, the method comprising:
- applying a first potential to a control gate of a first memory cell of a string of series-connected memory cells connected to a data line while activating each remaining memory cell of the string of series-connected memory cells;
generating a first output responsive to sensing the data line a first time while applying the first potential to the control gate of the first memory cell and while each remaining memory cell of the string of series-connected memory cells is activated;
applying a second potential to a control gate of a second memory cell of the string of series-connected memory cells while activating each remaining memory cell of the string of series-connected memory cells, wherein the second potential is generated as a function of the first output; and
sensing the data line a second time while applying the second potential to the control gate of the second memory cell and while each remaining memory cell of the string of series-connected memory cells is activated.
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Abstract
Devices, systems and methods for operating a memory device facilitating a neural network in a memory device are disclosed. In at least one embodiment, the memory device is operated having a feed-ward neural network operating scheme. In at least one other embodiment, memory cells are operated to emulate a number of neural models to facilitate one or more neural network operating characteristics in the memory device.
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Citations
67 Claims
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1. A method of operating a memory device, the method comprising:
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applying a first potential to a control gate of a first memory cell of a string of series-connected memory cells connected to a data line while activating each remaining memory cell of the string of series-connected memory cells; generating a first output responsive to sensing the data line a first time while applying the first potential to the control gate of the first memory cell and while each remaining memory cell of the string of series-connected memory cells is activated; applying a second potential to a control gate of a second memory cell of the string of series-connected memory cells while activating each remaining memory cell of the string of series-connected memory cells, wherein the second potential is generated as a function of the first output; and sensing the data line a second time while applying the second potential to the control gate of the second memory cell and while each remaining memory cell of the string of series-connected memory cells is activated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of operating a memory device, the method comprising:
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applying a first potential to a control gate of a first memory cell of a string of series-connected memory cells connected to a first data line and to a control gate of a first memory cell of a string of series-connected memory cells connected to a second data line while activating each remaining memory cell of the string of series-connected memory cells connected to the first data and each remaining memory cell of the string of series-connected memory cells connected to the second data line; generating first and second outputs responsive to sensing the first and second data lines a first time while applying the first potential to the control gate of the first memory cell of the string of series-connected memory cells connected to the first data line and to the control gate of the first memory cell of the string of series-connected memory cells connected to the second data line, and while each remaining memory cell of the string of series-connected memory cells connected to the first data line and each remaining memory cell of the string of series-connected memory cells connected to the second data line is activated; applying a second potential to a second memory cell of the string of series-connected memory cells connected to the first data line and to a second memory cell of the string of series-connected memory cells connected to the second data line while activating each remaining memory cell of the string of series-connected memory cells connected to the first data and each remaining memory cell of the string of series-connected memory cells connected to the second data line, wherein the second potential is generated as a function of at least one of the first and second outputs; and generating third and fourth outputs responsive to sensing the first and second data lines a second time while applying the second potential to the control gate of the second memory cell of the string of series-connected memory cells connected to the first data line and to the control gate of the second memory cell of the string of series-connected memory cells connected to the second data line, and while each remaining memory cell of the string of series-connected memory cells connected to the first data line and each remaining memory cell of the string of series-connected memory cells connected to the second data line is activated. - View Dependent Claims (13, 14, 15)
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16. A method of operating a memory device, the method comprising:
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applying a first potential to a control gate of a first memory cell of a first string of series-connected memory cells connected to a first data line while activating each remaining memory cell of the first string of series-connected memory cells; performing a first sense operation on the first data line responsive to applying the first potential to the control gate of the first memory cell of the first string of series-connected memory cells; generating a second potential, wherein the second potential comprises a potential level generated as a function of a first level sensed on the first data line during the first sense operation; applying the second potential to a control gate of a first memory cell of a second string of series-connected memory cells connected to a second data line while activating each remaining memory cell of the second string of series-connected memory cells; and performing a second sense operation on the second data line responsive to applying the second potential to the control gate of the first memory cell of the second string of series-connected memory cells. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A method of operating a memory device, the method comprising:
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applying a first potential to a first access line coupled to a first memory cell of a first string of series-connected memory cells and to a first memory cell of a second string of series-connected memory cells while activating each remaining memory cell of the first string of series-connected memory cells and each remaining memory cell of the second string of series-connected memory cells, wherein the first string of series-connected memory cells is connected to a first data line and where the second string of series-connected memory cells is connected to a second data line; applying a second potential to a second access line coupled to a first memory cell of a third string of series-connected memory cells and to a first memory cell of a fourth string of series-connected memory cells while activating each remaining memory cell of the third string of series-connected memory cells and each remaining memory cell of the fourth string of series-connected memory cells, wherein the third string of series-connected memory cells is connected to the first data line and where the fourth string of series-connected memory cells is connected to the second data line; concurrently sensing the first data line and the second data line while applying the first potential and the second potential; and generating a single output for a neuron model responsive to concurrently sensing the first and the second data lines. - View Dependent Claims (23)
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24. A method of operating a memory device as a neural network, the method comprising:
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performing a first sense operation on a first plurality of memory cells connected to a first data line and comprising a first neuron model, and generating a first output, wherein each memory cell of the first plurality of memory cells is contained in a different string of series-connected memory cells of a first plurality of strings of series-connected memory cells and wherein each memory cell of the first plurality of strings of series-connected memory cells other than the first plurality of memory cells is activated while performing the first sense operation; performing a second sense operation on a second plurality of memory cells connected to a second data line and comprising a second neuron model, and generating a second output, wherein each memory cell of the second plurality of memory cells is contained in a different string of series-connected memory cells of a second plurality of strings of series-connected memory cells and wherein each memory cell of the second plurality of strings of series-connected memory cells other than the second plurality of memory cells is activated while performing the second sense operation; performing a third sense operation on a third plurality of memory cells connected to the first data line and comprising a third neuron model, wherein each memory cell of the third plurality of memory cells is contained in a different string of series-connected memory cells of the first plurality of strings of series-connected memory cells and wherein each memory cell of the first plurality of strings of series-connected memory cells other than the third plurality of memory cells is activated while performing the third sense operation; and performing a fourth sense operation on a fourth plurality of memory cells connected to the second data line and comprising a fourth neuron model, wherein each memory cell of the fourth plurality of memory cells is contained in a different string of series-connected memory cells of the second plurality of strings of series-connected memory cells and wherein each memory cell of the second plurality of strings of series-connected memory cells other than the fourth plurality of memory cells is activated while performing the fourth sense operation; wherein the third sense operation is performed by applying a first and a second potential to the third neuron model where the first potential and the second potential are generated as a function of the first output and the second output; and wherein the fourth sense operation is performed by applying the first and the second potential to the fourth neuron model where the fourth sense operation is performed concurrently with the third sense operation.
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25. A memory device, comprising:
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a string of series-connected memory cells selectively connected to a data line; and a controller, wherein the controller is configured to apply a first potential to a control gate of a first memory cell of the string of series-connected memory cells during a first sense operation on the data line while activating each remaining memory cell of the string of series-connected memory cells and while the string of series-connected memory cells is connected to the data line, and to apply a second potential to a control gate of a second memory cell of the string of series-connected memory cells during a second sense operation on the data line while activating each remaining memory cell of the string of series-connected memory cells and while the string of series-connected memory cells is connected to the data line, wherein the second potential comprises a potential generated as a function of an output generated responsive to sensing the data line during the first sense operation. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A system, comprising:
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a communications channel; a memory access device coupled to the communications channel and configured to generate memory device commands; and a memory device coupled to the communications channel and configured to be responsive to the memory device commands, the memory device comprising; a string of series-connected memory cells selectively connected to a data line; and a controller, wherein the controller is configured to; apply a first potential to a control gate of a first memory cell of the string of series-connected memory cells during a first sense operation on the data line while activating each remaining memory cell of the string of series-connected memory cells and while the string of series-connected memory cells is connected to the data line; and apply a second potential to a control gate of a second memory cell of the string of series-connected memory cells during a second sense operation on the data line while activating each remaining memory cell of the string of series-connected memory cells and while the string of series-connected memory cells is connected to the data line, wherein the second potential comprises a potential generated as a function of an output generated responsive to sensing the data line during the first sense operation.
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43. A memory device, comprising:
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an array of memory cells comprising a plurality of NAND configured strings of series-connected memory cells; and a controller, wherein the controller is configured to operate at least a portion of the array of memory cells as a neural network; wherein the controller is further configured to operate a first plurality of memory cells of the array of memory cells as a first neuron model, wherein the first plurality of memory cells comprises at least two memory cells selectively connected to a particular data line, and wherein each of the at least two memory cells are contained in a different NAND configured string of series-connected memory cells each selectively connected to the particular data line; and wherein the controller is further configured to sense the particular data line while each of the at least two memory cells receives a respective potential at its control gate to selectively activate that memory cell of the at least two memory cells depending upon its data state, and while each remaining memory cell of the different NAND configured strings of series-connected memory cells containing a respective one of the at least two memory cells is activated, and while the particular data line is connected to each of the different NAND configured strings of series-connected memory cells containing a respective one of the at least two memory cells. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54)
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55. A method of operating a memory device as a neural network, the method comprising:
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stimulating a first plurality of memory cells of an array of memory cells comprising a plurality of strings of series-connected memory cells, wherein the first plurality of memory cells comprise a first neuron model, wherein the first plurality of memory cells comprises at least two memory cells selectively connected to a particular data line, and wherein each of the at least two memory cells are contained in a different string of a plurality of strings of series-connected memory cells; activating each remaining memory cell of each of the strings of the plurality of strings of series-connected memory cells while stimulating the first plurality of memory cells and while each of the strings of the plurality of strings of series-connected memory cells is connected to the particular data line; generating a first output responsive to stimulating the first plurality of memory cells while activating the remaining memory cells of the plurality of strings of series-connected memory cells; stimulating a second plurality of memory cells of the memory cells of the array of memory cells wherein the second plurality of memory cells comprise a second neuron model, wherein the second plurality of memory cells comprises at least two memory cells selectively connected to the particular data line, and wherein each of these at least two memory cells are contained in a different string of the plurality of strings of series-connected memory cells; and activating each remaining memory cell of each of the strings of the plurality of strings of series-connected memory cells while stimulating the second plurality of memory cells and while each of the strings of the plurality of strings of series-connected memory cells is connected to the particular data line; wherein the second plurality of memory cells are stimulated by applying the first output to the second plurality of memory cells. - View Dependent Claims (56, 57)
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58. A method of operating a memory device as a neural network, the method comprising:
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stimulating a first neuron model, wherein the first neuron model comprises a first plurality of memory cells of an array of memory cells of the memory device, wherein the first plurality of memory cells comprises at least two memory cells selectively connected to a particular data line, and wherein each of the at least two memory cells are contained in a different string of a plurality of strings of series-connected memory cells of the array of memory cells; activating each remaining memory cell of each of the strings of the plurality of strings of series-connected memory cells while stimulating the first neuron model and while each of the strings of the plurality of strings of series-connected memory cells is connected to the particular data line; generating a first output responsive to stimulating the first neuron model while activating the remaining memory cells of the plurality of strings of series-connected memory cells; stimulating a second neuron model, wherein the second neuron model comprises a second plurality of memory cells of the array of memory cells, wherein the second plurality of memory cells comprises at least two memory cells selectively connected to the particular data line, and wherein each of these at least two memory cells are contained in a different string of the plurality of strings of series-connected memory cells of the array of memory cells; and activating each remaining memory cell of each of the strings of the plurality of strings of series-connected memory cells while stimulating the second neuron model and while each of the strings of the plurality of strings of series-connected memory cells is connected to the particular data line; wherein the second neuron model is stimulated by applying the first output to the second neuron model. - View Dependent Claims (59, 60, 61, 62, 63, 64, 65, 66, 67)
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Specification