Volatile/non-volatile SRAM device

• US 9,431,097 B2
• Filed: 12/22/2014
• Issued: 08/30/2016
• Est. Priority Date: 12/22/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chen, Xiaonan, Wang, Zhongze, Li, Xia
• Primary Examiner(s): Le, Vu
• Application Number:
  US14/579,891
• Publication Number:
  US 20160180925A1
• Time in Patent Office: 617 Days
• Field of Search: 365/154, 365/156, 365/189.09
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell

Abstract

A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

Claims

1. A method of operation of a static random access memory (SRAM) storage element, the method comprising:

programming a value to the SRAM storage element prior to a power-down event; and

in response to a power-on event at the SRAM storage element after the power-down event;

increasing a supply voltage of the SRAM storage element; and

sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

2. The method of claim 1, wherein the SRAM storage element has a susceptibility to the state, and wherein the susceptibility is created by increasing a threshold voltage difference between transistors of the SRAM storage element.

3. The method of claim 2, wherein increasing the threshold voltage difference includes biasing a first body terminal of a first transistor of the SRAM storage element with a first bias voltage.

4. The method of claim 3, wherein increasing the threshold voltage difference further includes biasing a second body terminal of a second transistor of the SRAM storage element with a second bias voltage that is different than the first bias voltage.

5. The method of claim 4, wherein the first bias voltage is a positive voltage, and wherein the second bias voltage is a ground voltage.

6. The method of claim 2, wherein the susceptibility corresponds to either a first logic value associated with a set operation or a second logic value associated with a reset operation.

7. The method of claim 1, wherein sensing the state includes ramping the supply voltage from a low voltage level to a supply voltage level and detecting a voltage of a bit line coupled to the SRAM storage element.

8. The method of claim 1, further comprising applying a volatile operation biasing scheme to the SRAM storage element to operate the SRAM storage element as a volatile storage element.

9. The method of claim 1, wherein the supply voltage is provided by control circuitry coupled to the SRAM storage element.

10. The method of claim 9, wherein the SRAM storage element and the control circuitry are integrated within an electronic device selected from a mobile device, a computer, a set top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a television, a tuner, a radio, a music player, a video player, or a combination thereof.

11. An apparatus comprising:

a static random access memory (SRAM) storage element; and

control circuitry coupled to the SRAM storage element, the control circuitry configured to program a value to the SRAM storage element prior to a power-down event, the control circuitry further configured, in response to a power-on event at the SRAM storage element after the power-down event, to increase a supply voltage of the SRAM storage element and to sense a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

12. The apparatus of claim 11, wherein the control circuitry is further configured to create a susceptibility of the SRAM storage element to the state using a non-volatile operation biasing scheme.

13. The apparatus of claim 12, wherein the control circuitry is further configured to create the susceptibility using either a first biasing scheme to indicate a first logic value or a second biasing scheme to indicate a second logic value.

14. The apparatus of claim 13, wherein the control circuitry is further configured to bias a first body terminal of a first transistor of the SRAM storage element with a first bias voltage and to bias a second body terminal of a second transistor of the SRAM storage element with a second bias voltage that is different than the first bias voltage.

15. The apparatus of claim 14, wherein the first biasing scheme is used, and wherein the first bias voltage is a positive voltage, and wherein the second bias voltage is a ground voltage.

16. The apparatus of claim 14, wherein the second biasing scheme is used, and wherein the first bias voltage is a ground voltage, and wherein the second bias voltage is a positive voltage.

17. The apparatus of claim 13, wherein the control circuitry is further configured to sense the state using a third biasing scheme.

18. The apparatus of claim 11, wherein the control circuitry is further configured to operate the SRAM storage element as volatile storage using a volatile operation biasing scheme.

19. The apparatus of claim 11, further comprising an SRAM device, wherein the SRAM storage element and the control circuitry are integrated within the SRAM device.

20. The apparatus of claim 19, further comprising an electronic device selected from a mobile device, a computer, a set top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a television, a tuner, a radio, a music player, a video player, or a combination thereof, wherein the SRAM device is integrated within the electronic device.

21. An apparatus comprising:

means for accessing a static random access memory (SRAM) storage element; and

means for programming a value to the SRAM storage element prior to a power-down event, for increasing a supply voltage of the SRAM storage element in response to a power-on event at the SRAM storage element after the power-down event, and for sensing a state of the SRAM storage element after increasing the supply voltage to determine the value programmed to the SRAM storage element prior to the power-down event.

22. The apparatus of claim 21, wherein the means for accessing the SRAM storage element includes one or more word lines coupled to the SRAM storage element, one or more bit lines coupled to the SRAM storage element, or a combination thereof.

23. The apparatus of claim 21, wherein the means for increasing the supply voltage and for sensing the state includes control circuitry coupled to the SRAM storage element.

24. The apparatus of claim 21, further comprising an SRAM device, wherein the means for accessing the SRAM storage element and the means for increasing the supply voltage and for sensing the state are integrated within the SRAM device.

25. The apparatus of claim 24, further comprising an electronic device selected from a mobile device, a computer, a set top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a television, a tuner, a radio, a music player, a video player, or a combination thereof, wherein the SRAM device is integrated within the electronic device.