Memory die and method for efficient use of data latches in serving mixed traffic loads

• US 9,431,120 B1
• Filed: 03/23/2015
• Issued: 08/30/2016
• Est. Priority Date: 03/23/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Koh, Anne Pao-Ling, Manohar, Abhijeet, Tuers, Daniel E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/665,920
• Time in Patent Office: 526 Days
• Field of Search: 365/185.12, 365/185.05, 365/189.08
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A memory die is provided comprising a non-volatile memory organized in physical pages, a transfer data latch in communication with the non-volatile memory, at least one auxiliary data latch in communication with the transfer data latch, and circuitry. The circuitry is configured to receive a plurality of sense commands, wherein each sense command indicates a physical page in the non-volatile memory to be sensed and a portion of the physical page to be stored in the at least one auxiliary data latch. For each sense command, the circuitry is configured to store data from the physical page sensed by the sense command in the transfer data latch and move data from the portion of the physical page indicated by the sense command to an available location in the at least one auxiliary data latch.

Claims

1. A memory die comprising:

a non-volatile memory organized in physical pages;

a transfer data latch in communication with the non-volatile memory;

at least one auxiliary data latch in communication with the transfer data latch; and

circuitry in communication with the non-volatile memory, the transfer data latch, and the at least one auxiliary data latch, wherein the circuitry is configured to;

receive a plurality of sense commands, wherein each sense command indicates a physical page in the non-volatile memory to be sensed and a portion of the physical page to be stored in the at least one auxiliary data latch; and

for each sense command;

store data from the physical page sensed by the sense command in the transfer data latch; and

move data from the portion of the physical page indicated by the sense command to the at least one auxiliary data latch.

2. The memory die of claim 1, wherein each sense command indicates the portion of the physical page by indicating an offset and a length.

3. The memory die of claim 1, wherein the transfer data latch and the at least one auxiliary data latch are organized in tiers, and wherein data is moved from the transfer data latch to the at least one auxiliary data latch irrespective of whether the data would be moved to a different tier.

4. The memory die of claim 1, wherein the transfer data latch and the at least one auxiliary data latch are organized in tiers, and wherein data is moved between corresponding tiers in the transfer data latch and the at least one auxiliary data latch.

5. The memory die of claim 1, wherein the data is moved from the transfer data latch to the at least one auxiliary data latch using an input-output module.

6. The memory die of claim 1, wherein the non-volatile memory is a three-dimensional memory.

7. The memory die of claim 1, wherein the memory die is embedded in a host.

8. The memory die of claim 1, wherein the memory die is part of a memory system that is removably connected to a host.

9. A method comprising:

receiving a plurality of sense commands, wherein each sense command indicates a physical page in a non-volatile memory of a memory die having a first data latch and a second data latch to be sensed and a portion of the physical page to be stored in the second data latch; and

for each sense command;

latching data from the physical page sensed by the sense command in the first data latch; and

moving data from the portion of the physical page indicated by the sense command to the second data latch.

10. The method of claim 9, wherein each sense command indicates the portion of the physical page by indicating an offset and a length.

11. The method of claim 9, wherein the first and second data latches are organized in tiers, and wherein data is moved from the first data latch to the second data latch irrespective of whether the data would be moved to a different tier.

12. The method of claim 9, wherein the first and second data latches are organized in tiers, and wherein data is moved between corresponding tiers in the first and second data latches.

13. The method of claim 9, wherein the data is moved from the first data latch to the second data latch using an input-output module.

14. The method of claim 9, wherein the non-volatile memory is a three-dimensional memory.

15. The method of claim 9, wherein the memory die is embedded in a host.

16. The method of claim 9, wherein the memory die is part of a memory system that is removably connected to a host.

17. A memory die comprising:

a non-volatile memory organized in physical pages;

a first data latch configured to buffer a page of data sensed from one of the physical pages of the non-volatile memory;

a second data latch; and

a data latch control module in communication with the non-volatile memory and the first and second data latches, wherein the data latch control module is configured to transfer some but not all of the data from the first data latch to the second data latch.

18. The memory die of claim 17, wherein the data to be transferred is indicated by an offset and a length in a sense command.

19. The memory die of claim 17, wherein the first and second data latches are organized in tiers, and wherein data is transferred from the first data latch to the second data latch irrespective of whether the data would be transferred to a different tier.

20. The memory die of claim 17, wherein the first and second data latches are organized in tiers, and wherein data is transferred between corresponding tiers in the first and second data latches.

21. The memory die of claim 17, wherein the data is transferred from the first data latch to the second data latch using an input-output module.

22. The memory die of claim 17, wherein the non-volatile memory is a three-dimensional memory.

23. The memory die of claim 17, wherein the memory die is embedded in a host.

24. The memory die of claim 17, wherein the memory die is part of a memory system that is removably connected to a host.