One-time programmable memory and method for making the same

• US 9,431,254 B2
• Filed: 04/08/2015
• Issued: 08/30/2016
• Est. Priority Date: 06/21/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Kilopass Technology Incorporated (Synopsys Incorporated)
• Inventors: Luan, Harry Shengwen
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US14/681,852
• Publication Number:
  US 20150311215A1
• Time in Patent Office: 510 Days
• Field of Search: 257/209
• US Class Current: 1/1
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A one time programmable nonvolatile memory formed from metal-insulator semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting lines formed in a semiconductor substrate. Among others, features include forming the gate lines with polysilicon layers of one conductivity type and the intersecting lines with dopants of the opposite conductivity type in the substrate; forming the intersecting lines with differing dopant concentrations near the substrate surface and deeper in the substrate; and forming the widths of the gate lines and intersecting lines with the minimum feature size that can be patterned by a particular semiconductor technology.

Claims

1. A method of manufacturing a one-time programmable non-volatile memory cell comprising:

forming a buried bitline in a substrate, the buried bitline of a first conductivity type;

forming a dielectric layer over at least a portion of the buried bitline;

forming a polysilicon gate layer over at least a portion of the dielectric layer;

doping the polysilicon gate layer to cause the polysilicon gate layer to be a second conductivity type; and

after the doping, etching the polysilicon gate layer to form a conductive gate over the dielectric layer, the conductive gate formed over a channel region under the conductive gate and dielectric layer.

2. The method of claim 1 further including forming sidewall spacers on sidewalls of the conductive gate.

3. The method of claim 1 wherein the forming of the buried bitline is performed such that the buried bitline has a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

4. The method of claim 1 wherein the forming of the dielectric layer results in a dielectric layer that is thicker proximal to at least a portion of the edge of the channel region than to the center of the channel region.

5. A method of manufacturing an array of one-time programmable non-volatile memory cells, comprising:

forming a plurality of parallel buried bitlines in a substrate, each buried bitline of a first conductivity type, such that the buried bitline has a graded dopant concentration with a lower dopant concentration near the substrate surface and a higher dopant concentration deeper in the substrate;

forming a dielectric layer over at least a portion of the buried bitlines; and

forming a plurality of parallel metal gates over at least portions of the dielectric layer, each metal gate perpendicular to the buried bitlines and formed over a channel region under the metal gate and a portion of dielectric layer.

6. The method of claim 5 further including forming doped regions of the second conductivity type between channel regions under adjacent metal gates.

7. The method of claim 6 further including forming sidewall spacers on sidewalls of the metal gates and self-aligning the doped regions of first conductivity type with the sidewall spacers.

8. The method of claim 6 further including forming sidewall spacers on sidewalls of the plurality of metal gates and self-aligning the doped regions of second conductivity type with the sidewall spacers.

9. A method of manufacturing an array of one-time programmable non-volatile memory cells, comprising:

forming a plurality of buried bitlines in a substrate, each buried bitline having a deep layer of a first conductivity type and a shallow layer of second conductivity type;

forming a dielectric layer over at least a portion of the buried bitlines; and

forming a plurality of parallel metal gates over at least a portion of the dielectric layer, each metal gate perpendicular to the buried bitlines and formed over a channel region under the metal gate and dielectric layer.

10. The method of claim 9 further including forming doped regions of the first conductivity type, the doped regions being between channel regions under adjacent metal gates.

11. The method of claim 10 wherein the forming doped regions of first conductivity type step includes reaching the deep layer of first conductivity type of the buried bitline.

12. The method of claim 10 further including forming sidewall spacers on sidewalls of the plurality of metal gates and self-aligning the doped regions of first conductivity type with the sidewall spacers.

13. A method of manufacturing an array of one-time programmable non-volatile memory cells, the manufacturing method having a minimum feature size of F, comprising:

forming a plurality of buried bitlines of a first conductivity type in a substrate, each buried bitline having a defined width no more than F;

forming a dielectric layer over at least a portion of the buried bitlines; and

forming a plurality of metal gates over at least a portion of the dielectric layer, each metal gate perpendicular to the buried bitlines and having a defined width no more than F, the metal gate formed over a channel region under the metal gate and dielectric layer.

14. The method of claim 13 further comprising:

spacing the metal gates no more than F apart so that sidewall spacers conformally fills the space between adjacent metal gates.

15. The method of claim 13 wherein the forming of the plurality of buried bitlines is performed such that each buried bitline has a graded dopant concentration with a lower dopant concentration near the dielectric layer and a higher dopant concentration deeper in the substrate.

16. The method of claim 15 further including forming doped regions of the first conductivity type and having a dopant concentration higher than the lower dopant concentration of the buried bitlines, the doped regions being between channel regions under adjacent metal gates.

17. The method of claim 13 further including forming doped regions of the first conductivity type, the doped regions being between channel regions under adjacent metal gates.