Salicided structure to integrate a flash memory device with a high κ, metal gate logic device

• US 9,431,257 B2
• Filed: 07/14/2014
• Issued: 08/30/2016
• Est. Priority Date: 07/14/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ming Chyi
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US14/330,120
• Publication Number:
  US 20160013197A1
• Time in Patent Office: 778 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates. A silicide contact pad is arranged over a top surface of the first memory cell gate. The silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate and the metal gate. A method of manufacturing the integrated circuit is also provided.

Claims

1. An integrated circuit for an embedded flash memory device, said integrated circuit comprising:

a semiconductor substrate including a memory region and a logic region adjacent to the memory region;

a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9;

a flash memory cell device arranged over the memory region, wherein the flash memory cell device includes a first memory cell gate, a second memory cell gate, and a dielectric region arranged between neighboring sidewalls of the first and second memory cell gates, and wherein a top surface of the first memory cell gate is recessed below a top surface of the metal gate; and

a silicide contact pad arranged on the first memory cell gate, wherein the silicide contact pad is recessed relative to top surfaces of the dielectric region, the second memory cell gate, and the metal gate.

2. The integrated circuit according to claim 1, wherein the first memory cell gate is a memory gate, the second memory cell gate is a select gate, and the dielectric region includes a charge trapping dielectric arranged under the memory gate.

3. The integrated circuit according to claim 1, wherein the first memory cell gate is a word line or an erase gate, and the second memory cell gate is a control gate arranged over a floating gate.

4. The integrated circuit according to claim 1, wherein the flash memory cell device includes:

a floating gate;

an erase gate and a word line spaced from the floating gate on opposite sides of the floating gate;

a control gate arranged over the floating gate; and

a floating gate spacer arranged between neighboring sidewalls of the control gate, the word line, and the erase gate;

wherein the first memory cell gate is the word line or the erase gate, the second memory cell gate is the control gate, and the dielectric region includes the floating gate spacer.

5. The integrated circuit according to claim 1, further including:

a first interlayer dielectric substructure arranged over the silicide contact pad, wherein a top surface of the first interlayer dielectric substructure is coplanar with top surfaces of the metal gate and the second memory cell gate.

6. The integrated circuit according to claim 5, further including:

a contact etch stop arranged over the silicide contact pad between the first interlayer dielectric substructure and the silicide contact pad.

7. The integrated circuit according to claim 5, further including:

a second interlayer dielectric substructure independent of the first interlayer dielectric substructure and arranged over the first interlayer dielectric substructure, wherein a bottom surface of the second interlayer dielectric substructure is coplanar with the top surfaces of the metal gate and the second memory cell gate, and wherein the first and second interlayer dielectric substructures collectively cover the logic and memory regions.

8. The integrated circuit according to claim 1, further including:

a conductive contact extending vertically down to the silicide contact pad.

9. The integrated circuit according to claim 1, wherein the first memory cell gate includes a spacer arranged over an upper surface of the first memory cell gate, wherein the upper surface of the first memory cell gate is recessed below the top surface of the first memory cell gate.

10. An integrated circuit for an embedded flash memory device, said integrated circuit comprising:

a semiconductor substrate including a memory region and a logic region adjacent to the memory region, the memory region including a common source/drain region and a pair of individual source/drain regions arranged on opposite sides of the common source/drain region;

a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9; and

a pair of flash memory cell devices arranged over the memory region, wherein each flash memory cell device corresponds to one of the individual source/drain regions and includes;

a select gate and a memory gate arranged between the common source/drain region and the corresponding individual source/drain region;

a charge trapping dielectric arranged between neighboring sidewalls of the memory and select gates, and arranged under the memory gate; and

a silicide contact pad arranged over a top surface of the memory gate, wherein a top surface of the silicide contact pad is recessed relative to top surfaces of the charge trapping dielectric, the select gate, and the metal gate.

11. The integrated circuit according to claim 10, wherein each flash memory cell device further comprises:

a first interlayer dielectric substructure arranged over the silicide contact pad, wherein a top surface of the first interlayer dielectric substructure is coplanar with top surfaces of the metal gate and the select gate.

12. The integrated circuit according to claim 11, further comprising:

a contact etch stop arranged over the silicide contact pad between the first interlayer dielectric substructure and the silicide contact pad.

13. The integrated circuit according to claim 11, further comprising:

a second interlayer dielectric substructure independent of the first interlayer dielectric substructure and arranged over the first interlayer dielectric substructure, wherein a bottom surface of the second interlayer dielectric substructure is coplanar with top surfaces of the metal gate and the select gate, and wherein the first and second interlayer dielectric substructures collectively cover the logic and memory regions.

14. The integrated circuit according to claim 10, wherein each flash memory cell device further comprises a spacer arranged over an upper surface of the memory gate, wherein the upper surface of the memory gate is laterally adjacent to the top surface of the memory gate and is recessed below the top surface of the memory gate.

15. An integrated circuit comprising:

a logic device arranged on a semiconductor substrate, wherein the logic device comprises a metal gate arranged over and spaced from the semiconductor substrate;

a memory cell device arranged on the semiconductor substrate and laterally spaced from the logic device, wherein the memory cell device includes a first memory cell gate laterally spaced from a second memory cell gate; and

a silicide contact pad arranged on a top surface of the first memory cell gate and recessed below substantially coplanar top surfaces of the metal and second memory cell gates.

16. The integrated circuit according to claim 15, wherein the second memory cell gate is a select gate.

17. The integrated circuit according to claim 16, further comprising:

a charge trapping dielectric layer arrange between neighboring sidewalls of the first and second memory cell gates, and further arranged under the first memory cell gate.

18. The integrated circuit according to claim 15, wherein the first memory cell gate is a word line or an erase gate, and wherein the second memory cell gate is a control gate arranged over a floating gate.

19. The integrated circuit according to claim 15, wherein the first memory cell gate comprises an upper surface that is laterally adjacent to the top surface of the first memory cell gate and that is recessed below the top surface of the first memory cell gate.

20. The integrated circuit according to claim 15, further comprising:

an interlayer dielectric structure arranged over the silicide contact pad, wherein a top surface of the interlayer dielectric structure is coplanar with the top surfaces of the metal and second memory cell gates; and

a contact etch stop arranged over the silicide contact pad between the interlayer dielectric structure and the silicide contact pad.