Semiconductor device and manufacturing method of the same

• US 9,431,260 B2
• Filed: 12/08/2014
• Issued: 08/30/2016
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Original Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Inventors: Oka, Tohru, Tanaka, Nariaki
• Primary Examiner(s): OLSEN, ALLAN W
• Application Number:
  US14/563,943
• Publication Number:
  US 20150162208A1
• Time in Patent Office: 631 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/3245 of AIIIBV compounds

Abstract

There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer.

Claims

1. A manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer, the manufacturing method comprising:

a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction in order to expose a surface of the P-type semiconductor layer; and

an annealing process of annealing the P-type semiconductor layer in an atmosphere comprising oxygen, after the dry etching process,

wherein a width of the P-type semiconductor layer exposed by the dry etching process is not less than 1% of a half pitch of the semiconductor device.

2. The manufacturing method of the semiconductor device according to claim 1, wherein the P-type semiconductor layer and the N-type semiconductor layer are mainly made of gallium nitride.

3. The manufacturing method of the semiconductor device according to claim 1, wherein a width of the P-type semiconductor layer exposed by the dry etching process is not less than 1 μ

m.

4. The manufacturing method of the semiconductor device according to claim 1, wherein the half pitch of the semiconductor device is not greater than 10 μ

m.

5. The manufacturing method of the semiconductor device according to claim 1, wherein the annealing process has an annealing temperature of not lower than 800°

C. and an a annealing time of not shorter than 5 minutes and not longer than 60 minutes.

6. The manufacturing method of the semiconductor device according to claim 1, wherein the surface of the P-type semiconductor layer exposed by the dry etching process comprises a c plane.

7. The manufacturing method of the semiconductor device according to claim 1, further comprising:

forming the P-type semiconductor layer and the N-type semiconductor layer by metal organic chemical vapor deposition (MOCVD).

8. The manufacturing method of the semiconductor device according to claim 1, wherein a molar fraction of gallium nitride in the P-type semiconductor layer and the N-type semiconductor layer is 90% or greater.

9. The manufacturing method of the semiconductor device according to claim 1, wherein the performing of the dry etching comprises forming a plurality of recesses in the N-type semiconductor layer, the surface of the P-type semiconductor layer being exposed through a first recess of the plurality of recesses.

10. The manufacturing method of the semiconductor device according to claim 9, further comprising:

forming an other N-type semiconductor layer on a substrate, the P-type semiconductor layer being formed on the other N-type semiconductor layer,

wherein a second recess of the plurality of recesses comprises a trench having a bottom which is formed in the other N-type semiconductor layer.

11. The manufacturing method of the semiconductor device according to claim 10, further comprising:

forming a body electrode on the surface of the P-type semiconductor layer in the first recess;

forming a drain electrode on a surface of the substrate which is opposite the other N-type semiconductor layer;

forming a source electrode on the N-type semiconductor layer between the first recess and the second recess; and

forming a gate electrode on the insulating film in the trench.

12. The manufacturing method of the semiconductor device according to claim 1, wherein the performing of the dry etching comprises performing inductively coupled plasma (ICP) dry etching of the semiconductor device in an atmosphere comprising at least one of chlorine and chlorides.

13. The manufacturing method of the semiconductor device according to claim 1, wherein the annealing of the P-type semiconductor layer comprises annealing the P-type semiconductor layer in a gas comprising oxygen and nitrogen, a temperature of the gas is not greater than 1000°

C., and a ratio of a flow rate of oxygen to a flow rate of nitrogen of the gas is not less than 1%.

14. A method of manufacturing a semiconductor device, comprising:

forming a first N-type semiconductor layer on substrate;

forming a P-type semiconductor layer on the first N-type semiconductor layer;

forming a second N-type semiconductor layer on the P-type semiconductor layer;

performing a dry etching of the second N-type semiconductor layer to form a plurality of recesses in the N-type semiconductor layer, the surface of the P-type semiconductor layer being exposed through a first recess of the plurality of recesses; and

after the performing of the drying etching, annealing the P-type semiconductor layer in an atmosphere comprising oxygen,

wherein a width of the surface of the P-type semiconductor layer exposed by the dry etching is not less than 1% of a half pitch of the semiconductor device, the half pitch comprising a distance between a center axis of a first recess and a center axis of a second recess of the plurality of recesses.