Power semiconductor package with gate and field electrode leads

• US 9,431,394 B2
• Filed: 08/29/2013
• Issued: 08/30/2016
• Est. Priority Date: 08/29/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US14/013,804
• Publication Number:
  US 20150061003A1
• Time in Patent Office: 1,097 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40247 Connecting the strap to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73263 Layer and strap connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/404 : Multiple field plate structures
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7397 : and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A power semiconductor package includes a housing, a semiconductor chip embedded in the housing, and at least four terminals partially embedded in the housing and partially exposed to the outside of the housing. The semiconductor chip includes a first doping region in ohmic contact with a first metal layer, a second doping region in ohmic contact with a second metal layer, and a plurality of first trenches that includes gate electrodes and first field electrodes electrically insulated from the gate electrodes. A first terminal of the four terminals is electrically connected to the first metal layer, a second terminal of the four terminals is electrically connected to the second metal layer, a third terminal of the four terminals is electrically connected to the gate electrodes of the first trenches, and a fourth terminal of the four terminals is electrically connected to the first field electrodes of the first trenches.

Claims

1. A power semiconductor package, comprising:

a housing;

a semiconductor chip at least partially embedded in the housing, the semiconductor chip comprising a first doping region in ohmic contact with a first metal layer, a second doping region in ohmic contact with a second metal layer, and at least a. plurality of first trenches formed in the semiconductor chip, wherein the first trenches comprise gate electrodes and at least first field electrodes electrically insulated from the gate electrodes; and

at least four terminals partially embedded in the housing and partially exposed to the outside of the housing, wherein

a first terminal of the at least four terminals is electrically connected to the first metal layer,

a second terminal of the at least four terminals is electrically connected to the second metal layer,

a third terminal of the at least four terminals is electrically connected to the gate electrodes of the first trenches, and

a fourth terminal of the at least four terminals is electrically connected to the first field electrodes of the first trenches.

2. The power semiconductor package of claim 1, wherein the first metal layer is arranged on a first side of the semiconductor chip, and the second metal layer is arranged on a second side of the semiconductor chip arranged opposite the first side of the semiconductor chip.

3. The power semiconductor package of claim 1, further comprising

a plurality of second trenches formed in the semiconductor chip, wherein the second trenches comprise gate electrodes and at least field electrodes electrically insulated from the gate electrodes of the second trenches, wherein the gate electrodes of the second trenches are electrically connected with the third terminal;

and

a fifth terminal partially embedded in the housing and exposed to the outside of the housing, wherein the fifth terminal is electrically connected to the field electrodes of the second trenches.

4. The power semiconductor package of claim 1, wherein the first trenches comprise at least second field electrodes electrically insulated from the gate electrodes and the first field electrodes, wherein the power semiconductor package further comprises:

a fifth terminal partially embedded in the housing and exposed to the outside of the housing, wherein the fifth terminal is electrically connected to the second field electrodes of the first trenches.

5. The power semiconductor package of claim 1, further comprising

a plurality of second trenches formed in the semiconductor chip, wherein the second trenches comprise gate electrodes without field electrodes, and wherein the gate electrodes of the second trenches are electrically connected to the third terminal.

6. The power semiconductor package of claim 1, further comprising

a plurality of second trenches formed in the semiconductor chip, wherein the second trenches comprise gate electrodes and at least field electrodes, and wherein the gate electrodes of the second trenches are electrically connected to the third terminal, and the field electrodes of the second trenches are electrically connected to the first doping region.

7. The power semiconductor package of claim 1, further comprising a first bond connection comprising at least one bond wire that electrically connects the first metal layer with the first terminal, wherein the bond wire is embedded in the housing.

8. The power semiconductor package of claim 1, further comprising:

a gate metallization in ohmic contact with the gate electrodes of the first trenches; and

a second bond connection comprising at least one bond wire that electrically connects the gate metallization with the third terminal, wherein the bond wire is embedded in the housing.

9. The power semiconductor package of claim 1, further comprising:

a first field electrode metallization in ohmic contact with the field electrode of the first trenches; and

a third bond connection comprising at least one bond wire that electrically connects the first field electrode metallization with the fourth terminal, wherein the bond wire is embedded in the housing.

10. The power semiconductor package of claim 1, wherein the second metal layer is soldered to the second terminal.

11. The power semiconductor package of claim 1, wherein the first terminal comprises a die attachment pad, and wherein the first metal layer is soldered to the die attachment pad.

12. The power semiconductor package of claim 11, further comprising a metal clip soldered to the first metal layer, wherein the first terminal comprises a connection pad that is electrically connected to the metal clip.

13. The power semiconductor package of claim 1, wherein the housing is made of an organic molding material.

14. The power semiconductor package of claim 1, wherein the first doping region of the semiconductor chip forms a source region of a FET and the second doping region of the semiconductor chip forms a drain region of the FET, wherein the semiconductor chip further comprises a body region which is complementary doped to the source region.

21. The power semiconductor package of claim 1, wherein the first doping region is a source or emitter region of a power FET, wherein the second doping region is a drain or collector region of a power FET, and wherein the first field electrodes of the first trenches and the fourth terminal are electrically independent from the first doping region and the second doping region.

15. A power semiconductor package, comprising:

a housing;

a semiconductor chip embedded in the housing, the semiconductor chip comprising a first doping region in ohmic contact with a first metal layer arranged on a first side of the semiconductor chip, a second doping region in ohmic contact with a second metal layer arranged on a second side of the semiconductor chip that is opposite the first side, and a plurality of trenches formed in the semiconductor chip, wherein the trenches comprise gate electrodes and at least first field electrodes electrically insulated from the gate electrodes; and

at least four terminals partially embedded in the housing and partially exposed to the outside of the housing, wherein

a first terminal of the at least four terminals is electrically connected to the first metal layer,

a second terminal of the at least four terminals is electrically connected to the second metal layer,

a third terminal of the at least four terminals is electrically connected to the gate electrodes of the trenches, and

a fourth terminal of the at least four terminals is electrically connected to the first field electrode of every nth numbered trench of the trenches, and electrically insulated from the first field electrodes of the other trenches, wherein n is equal to or larger than 2.

16. The power semiconductor package of claim 15, further comprising

a fifth terminal partially embedded in the housing and exposed to the outside of the housing, wherein the fifth terminal is electrically connected to at least some of the first field electrodes of the trenches that are electrically insulated from the fourth terminal.

17. The power semiconductor package of claim 15, wherein at least some of the first field electrodes of the trenches that are electrically insulated from the fourth terminal are electrically connected to the first doping region.

18. The power semiconductor package of claim 15, wherein the first doping region forms a source region and a second doping region forms a drain region, the semiconductor chip further comprising:

a body region that is complementary doped to the source region, and a drift region of the same conductivity type as the source region and arranged between the body region and the drain region, wherein the trenches extends from the first side to the drift region.

19. The power semiconductor package of claim 15, wherein n is equal to or larger than 3.

20. The power semiconductor package of claim 15, wherein the semiconductor chip further comprises:

an active area, an outer rim and an edge termination area arranged between the active area and the outer rim; and

a termination structure arranged in the edge termination area, wherein the termination structure comprises at least one of a doping region, a field electrode and a potential ring;

wherein the semiconductor package includes a fifth terminal partially embedded in the housing and partially exposed to the outside of the housing, wherein the fifth terminal is electrically connected to the termination structure.

22. The power semiconductor package of claim 15, wherein the first doping region is a source or emitter region of a power FET, wherein the second doping region is a drain or collector region of a power FET, and wherein the first field electrode of every nth numbered trench and the fourth terminal are electrically independent from the first doping region and the second doping region.