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Memory device comprising electrically floating body transistor

  • US 9,431,401 B2
  • Filed: 04/14/2015
  • Issued: 08/30/2016
  • Est. Priority Date: 03/09/2013
  • Status: Active Grant
First Claim
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1. A semiconductor memory array comprising at least two memory cells, wherein each said memory cell comprises:

  • a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

    a first region in electrical contact with said floating body region;

    a second region in electrical contact with said floating body region and spaced apart from said first region;

    a gate positioned between said first and second regions;

    a first insulating region located above said floating body region;

    second insulating regions adjacent to said floating body region; and

    a buried layer region located below said floating body region and said second insulating regions;

    wherein at least one of said floating body regions is integral with or connected to another of said floating body regions.

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