Memory device comprising electrically floating body transistor

• US 9,431,401 B2
• Filed: 04/14/2015
• Issued: 08/30/2016
• Est. Priority Date: 03/09/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Widjaja, Yuniarto
• Primary Examiner(s): Ngo, Ngan
• Application Number:
  US14/685,827
• Publication Number:
  US 20150221653A1
• Time in Patent Office: 504 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

Claims

1. A semiconductor memory array comprising at least two memory cells, wherein each said memory cell comprises:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region; and

a buried layer region located below said floating body region and said second insulating regions;

wherein at least one of said floating body regions is integral with or connected to another of said floating body regions.

2. The semiconductor memory array of claim 1, wherein each said memory cell further comprises a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

3. The semiconductor memory array of claim 1, wherein said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said second region has said first conductivity type;

said floating body region has a second conductivity type selected from a p-type conductivity type and an n-type conductivity type and different from said first conductivity type; and

said buried layer region has said first conductivity type.

4. The semiconductor memory array of claim 1, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

5. The semiconductor memory array of claim 1, wherein said floating body region, said first region, said second region, said gate, said first insulating region, said second insulating regions and said buried layer form a memory device;

and

wherein each said semiconductor memory cell further comprises an access transistor connected in series with said memory device.

6. A semiconductor memory array comprising at least two memory cells, wherein each said memory cell comprises:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region; and

a buried layer region located below said floating body region and said second insulating regions,

wherein at least one of said floating body regions is integral with or connected to another of said floating body regions; and

wherein a depletion region formed as a result of an application of a back bias to said buried layer region and at least one of said second insulating regions adjacent to said floating body region insulate said memory cell from an adjacent memory cell.

7. The semiconductor memory array of claim 6, wherein each said memory cell further comprises a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

8. The semiconductor memory array of claim 6, wherein said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said second region has said first conductivity type;

said floating body region has a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and different from said first conductivity type; and

said buried layer region has said first conductivity type.

9. The semiconductor memory cell of claim 6, wherein said back bias is applied as a constant positive voltage bias.

10. The semiconductor memory cell of claim 6, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

11. The semiconductor memory cell of claim 6, wherein said floating body region, said first region, said second region, said gate, said first insulating region, said second insulating regions and said buried layer form a memory device;

and

wherein said semiconductor memory cell further comprises an access transistor connected in series with said memory device.

12. A semiconductor memory array comprising at least two memory cells, wherein each said memory cell comprises:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region; and

a buried layer region located below said floating body region and said second insulating regions,

wherein at least one of said floating body regions is integral with or connected to another of said floating body regions;

wherein a depletion region formed as a result of an application of a back bias to said buried layer region and at least one of said second insulating regions adjacent to said floating body region insulate said memory cell from an adjacent memory cell, and

wherein application of said back bias results in at least two stable floating body charge levels.

13. The semiconductor memory array of claim 12, wherein each said memory cell further comprises a substrate region, wherein said buried layer region is positioned between said substrate region and said floating body region.

14. The semiconductor memory array of claim 12, wherein said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said second region has said first conductivity type;

said floating body region has a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and different from said first conductivity type; and

said buried layer region has said first conductivity type.

15. The semiconductor memory cell of claim 12, wherein said back bias is applied as a constant positive voltage bias.

16. The semiconductor memory cell of claim 12, wherein said buried layer region is configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell.

17. The semiconductor memory cell of claim 12, wherein said floating body region, said first region, said second region, said gate, said first insulating region, said second insulating regions and said buried layer form a memory device;

and

wherein said semiconductor memory cell further comprises an access transistor connected in series with said memory device.