Semiconductor device with vertical memory

• US 9,431,415 B2
• Filed: 11/06/2014
• Issued: 08/30/2016
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae-duk, Shin, Yoo-cheol, Park, Young-woo
• Primary Examiner(s): Bradford, Peter
• Application Number:
  US14/534,352
• Publication Number:
  US 20150129878A1
• Time in Patent Office: 663 Days
• Field of Search: 257/66
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Claims

1. A semiconductor device, comprising:

a driving circuit region on a substrate to control driving signals;

a polysilicon layer on the driving circuit region;

a memory cell array region on the polysilicon layer and overlapping the driving circuit region, the driving circuit region being under the memory cell array region;

an upper interconnection layer on the memory cell array region; and

a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the driving circuit region.

2. The semiconductor device as claimed in claim 1, wherein the driving circuit region includes at least one driving circuit configured to process input or output data.

3. The semiconductor device as claimed in claim 2, wherein the at least one driving circuit includes a page buffer, a latch circuit, a cache circuit, a column decoder, a sense amplifier, or a data in/out circuit.

4. The semiconductor device as claimed in claim 1, wherein the upper interconnection layer includes copper, aluminum, silver, or gold.

5. A semiconductor device, comprising:

a driving circuit gate structure on a substrate to control driving signals;

a first semiconductor layer on the driving circuit gate structure;

a memory cell array region on the first semiconductor layer;

a vertical contact through the memory cell array region and the first semiconductor layer, the vertical contact being electrically connected to the driving circuit gate structure; and

a driving circuit interconnection structure including an upper interconnection layer on the memory cell array region, the driving circuit interconnection structure being electrically connected to the vertical contact.

6. The semiconductor device as claimed in claim 5, wherein the driving circuit gate structure overlaps the memory cell array region in a vertical direction.

7. The semiconductor device as claimed in claim 5, wherein the driving circuit interconnection structure further comprises a dummy bit line at a same level as a bit line in the memory cell array region, the vertical contact and the upper interconnection layer being electrically connected to each other through the dummy bit line.

8. The semiconductor device as claimed in claim 5, wherein the driving circuit interconnection structure further comprises a lower interconnection layer connected to the driving circuit gate structure under the memory cell array region, the upper interconnection layer including a material having a lower sheet resistance than a material of the lower interconnection layer.

9. The semiconductor device as claimed in claim 5, wherein the memory cell array region includes:

a channel layer extending in a vertical direction on the first semiconductor layer; and

a ground selection line, word lines, and a string selection line spaced apart in the vertical direction along a sidewall of the channel layer.

10. The semiconductor device as claimed in claim 5, wherein the first semiconductor layer includes at least one source region, the at least one source region being electrically connected to the substrate through a first buried contact.

11. The semiconductor device as claimed in claim 10, wherein the at least one source region includes a first impurity, a concentration of the first impurity in the at least one source region increases in a vertical direction toward the substrate.

12. The semiconductor device as claimed in claim 10, wherein the first buried contact and the at least one source region extend in a same direction.

13. The semiconductor device as claimed in claim 5, wherein the first semiconductor layer includes at least one p+ well, the at least one p+ well being electrically connected to the substrate through a second buried contact.

14. The semiconductor device as claimed in claim 5, further comprising a barrier metal layer between the first semiconductor layer and the driving circuit gate structure.

15. The semiconductor device as claimed in claim 5, wherein the memory cell array region includes:

a plurality of word lines on the first semiconductor layer and spaced apart from the first semiconductor layer; and

a ground selection line and a string selection line on two sides of the plurality of word lines, respectively.

16. A semiconductor device, comprising:

a memory cell array region on a substrate;

a driving circuit gate structure between the memory cell array region and the substrate to control driving signals, the memory cell array region and the driving circuit gate structure overlapping each other;

a first semiconductor layer between the driving circuit gate structure and the memory cell array region;

a vertical contact through the memory cell array region and through the first semiconductor layer, the vertical contact being electrically connected to the driving circuit gate structure; and

a driving circuit interconnection structure on the memory cell array region, the driving circuit interconnection structure being electrically connected to the vertical contact.

17. The semiconductor device as claimed in claim 16, wherein the memory cell array region is spaced apart from the driving circuit gate structure along a vertical direction, the memory cell array region completely overlapping the driving circuit gate structure.

18. The semiconductor device as claimed in claim 17, wherein the vertical contact extends along the vertical direction through the memory cell array region and through the first semiconductor layer, the vertical contact electrically connecting the driving circuit interconnection structure and the driving circuit gate structure through the memory cell array region.

19. The semiconductor device as claimed in claim 16, wherein the first semiconductor layer includes at least one source region electrically connected to the substrate through a first buried contact, the first buried contact overlapping the memory cell array region.

20. The semiconductor device as claimed in claim 19, wherein the first semiconductor layer is spaced apart from the substrate along a vertical direction, the first buried contact extending along the vertical direction from the first semiconductor layer toward the substrate.