Package of finger print sensor and fabricating method thereof

• US 9,431,447 B2
• Filed: 08/04/2015
• Issued: 08/30/2016
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Jin Young, Park, No Sun, Kim, Yoon Joo, Lee, Seung Jae, Cha, Se Woong, Kim, Sung Kyu, Yoon, Ju Hoon
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US14/817,477
• Publication Number:
  US 20150340399A1
• Time in Patent Office: 392 Days
• US Class Current: 1/1
• CPC Class Codes: G06V 40/12 Fingerprints or palmprints
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14678 Contact-type imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect

Abstract

Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Claims

1. A semiconductor device comprising:

a semiconductor die comprising a first surface, a second surface opposite the first surface, and side surfaces connecting the first and second surfaces, where the first surface comprises a fingerprint sensor circuit and a plurality of bond pads;

an encapsulant surrounding the side surfaces, but not the first and second surfaces, of the semiconductor die;

a first lower passivation layer covering at least a portion of the first surface of the semiconductor die and comprising openings that expose the bond pads;

first redistribution layers (RDLs) electrically connected to the bond pads exposed through the first lower passivation layer;

a first upper passivation layer covering at least a portion of the second surface of the semiconductor die;

a plurality of vias electrically connected to the first RDLs at a first end of the vias and passing through the encapsulant;

second RDLs electrically connected to a second end of the vias and formed on the first upper passivation layer;

a second upper passivation layer exposing first portions of the second RDLs and covering second portions of the second RDLs and at least a portion of the encapsulant; and

electrical connection structures coupled to the exposed first portions of the second RDLs.

2. The semiconductor device of claim 1, wherein the first RDLs extend outside a footprint of the semiconductor die.

3. The semiconductor device of claim 1, wherein the first lower passivation layer and the encapsulant are made of a same material.

4. The semiconductor device of claim 1, comprising a second lower passivation layer covering the first lower passivation layer and the first RDLs.

5. The semiconductor device of claim 4, wherein the first lower passivation layer, the second lower passivation layer, and the encapsulant are made of a same material.

6. The semiconductor device of claim 1, wherein at least one of the first RDLs comprises a ground pattern for protecting the finger print sensor circuit against electrostatic discharge.

7. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises fingerprint sensor circuitry and a bond pad;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connecting the bond pad to a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via;

an electrical interconnection structure coupled to the second conductive layer; and

a first dielectric layer between the first conductive layer and the first die surface and between the first conductive layer and the first encapsulant surface, wherein the first dielectric layer comprises a first aperture through which the first conductive layer and the bond pad are connected and a second aperture through which the first conductive layer and the first end of the conductive via are connected.

8. The semiconductor device of claim 7, comprising a second dielectric layer that covers the first conductive layer and the first dielectric layer.

9. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises fingerprint sensor circuitry and a bond pad, and wherein the fingerprint sensor circuitry comprises image sensor circuitry;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connecting the bond pad to a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via; and

an electrical interconnection structure coupled to the second conductive layer.

10. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises fingerprint sensor circuitry and a bond pad, and wherein the semiconductor die is rectangular shaped with a first and second of the side die surfaces longer than a third and fourth of the side die surfaces;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connecting the bond pad to a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via;

an electrical interconnection structure coupled to the second conductive layer;

a first dielectric layer that covers the first die surface; and

a first conductive trace, wherein;

the first conductive trace runs in a plane that is parallel to the first die surface and separated from the first die surface by at least the first dielectric layer; and

the first conductive trace runs alongside the first side die surface along at least most of the length of the first side die surface.

11. The semiconductor device of claim 10, wherein the first conductive trace is positioned to electrically interact with a finger contacting the semiconductor device.

12. The semiconductor device of claim 10, comprising a second conductive trace, wherein:

the second conductive trace runs in the plane that is parallel to the first die surface and separated from the first die surface by at least the first dielectric layer;

the second conductive trace runs alongside the second side die surface along at least most of the length of the second side die surface.

13. The semiconductor device of claim 10, wherein the first conductive trace comprises a first portion that runs parallel to the first side die surface, and a second portion that runs diagonal to the first side die surface.

14. The semiconductor device of claim 13, wherein the first conductive trace comprises a third portion that runs perpendicular to the first side die surface.

15. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises fingerprint sensor circuitry and a bond pad;

an encapsulant surrounding at least the side die surfaces;

a first dielectric layer covering the first die surface and comprising an opening that exposes the bond pad;

a first conductive layer electrically connected to the bond pad exposed through the first dielectric layer;

a conductive via electrically connected to the first conductive layer at a first end of the via and passing through the encapsulant;

a second conductive layer electrically connected to a second end of the via; and

an electrical interconnection structure coupled to the second conductive layer.

16. The semiconductor device of claim 15, wherein the fingerprint sensor circuitry comprises a fingerprint capture sensor configured for fingerprint capture off a fingerprint touch.

17. The semiconductor device of claim 15, wherein the semiconductor die is rectangular shaped with a first and second of the side die surfaces longer than a third and fourth of the side die surfaces, and the semiconductor device comprises a first conductive trace, wherein:

the first conductive trace runs in a plane that is parallel to the first die surface and separated from the first die surface by at least the first dielectric layer; and

the first conductive trace runs alongside the first side die surface along at least most of the length of the first side die surface.

18. The semiconductor device of claim 17, comprising a second conductive trace, wherein:

the second conductive trace runs in the plane that is parallel to the first die surface and separated from the first die surface by at least the first dielectric layer;

the second conductive trace runs alongside to the second side die surface along at least most of the length of the second side die surface.

19. The semiconductor device of claim 18, wherein at least one of the first conductive trace and the second conductive trace is grounded.

20. The semiconductor device of claim 17, wherein the first conductive trace comprises a first portion that runs parallel to the first side die surface, and a second portion that runs diagonal to the first side die surface.