Method of forming SGT MOSFETs with improved termination breakdown voltage

• US 9,431,495 B2
• Filed: 08/08/2014
• Issued: 08/30/2016
• Est. Priority Date: 08/08/2014
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Ding, Yongping, Lee, Yeeheng, Wang, Xiaobin, Bobde, Madhur
• Primary Examiner(s): Luu, Chuong A
• Application Number:
  US14/455,150
• Publication Number:
  US 20160043192A1
• Time in Patent Office: 753 Days
• Field of Search: 438/259, 438/270, 438/589, 438/427, 438/386, 438/388, 438/689, 438/734, 438/735, 438/736, 438/749, 438/424, 438/426, 438/425, 438/429, 438/443, 438/700, 438/738, 438/271, 438/587, 438/588
• US Class Current: 1/1
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the termination trench and performing a second etching to increase the depth of the active trench to a desired depth wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller than a depth difference between the initial depth of the active trench and the desired depth of the termination trench.

Claims

1. A method for preparing a trench power semiconductor device comprising:

providing a semiconductor substrate comprising a bottom substrate and an epitaxial layer formed atop the bottom substrate;

performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is less than the desired depth of the termination trench;

applying a mask to cover the termination trench but exposing the active trench;

performing a second etching to increase the depth of the active trench to a desired depth of the active trench, wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller less than a depth difference between the initial depth of the active trench and the desired depth of the termination trench;

forming an insulating layer lining bottom and sidewalls of the active trench and the termination trench;

filling a conductive material into the active trench and the termination trench;

etching back the conductive material in an upper portion of the active trench and the termination trench leaving only the conductive material in the lower portion of the active trench and the termination trench;

filling the upper portion of the active trench and the termination trench with an insulating material;

etching back a top portion of the insulating material in the active trench and a portion of the insulting material on sidewall of the termination trench near the active area forming an insulating layer on top of the conductive material in the lower portion of the active trench and the termination trench and a remaining portion of the insulating layer at the sidewall of the termination trench farther from the active area; and

forming another insulating layer lining on exposed sidewall on the upper portion of the active trench and the termination trench and then filling the upper portion of the active trench and the termination trench with a conductive material.

2. The method of claim 1, wherein the step of performing a first etching of the epitaxial layer comprises:

applying a first hard mask layer over the semiconductor substrates;

forming openings therein, wherein an opening for the active trench is smaller than an opening for the termination trench; and

performing the first etching of the epitaxial layer through the opening for the active trench and opening for the termination trench to form the termination trench and the active trench, wherein the termination trench is wider than the active trench, and wherein an etch rate of forming the termination trench is faster than an etch rate of forming the active trench, the desired depth of termination trench is greater than the initial depth of the active trench.

3. The method of claim 1 further comprising:

implanting a top portion of the epitaxial layer with dopants of a conductivity type opposite to that of the semiconductor substrate to form a body layer surrounding the upper portion of the active trench and the termination trench; and

implanting dopants of a same conductivity type as the semiconductor substrate into a top portion of the body layer in the active area to form a source layer surrounding the upper portion of the active trench.

4. The method of claim 1, wherein after the step of filling the upper portion of each active trench and the termination trench with an insulating material and before the step of etching back a top portion of the insulating material in the active trench and a portion of the insulting material at the sidewall of the termination trench close to the active area further comprises:

applying a mask to cover a portion of the insulting material at the sidewall of the termination trench farther from the active area, whereas the portion of the insulting material at the sidewall of the termination trench close to the active area is exposed from the mask, wherein the conductive material filled in the upper portion of the termination trench is offset to the active area.

5. The method of claim 1, wherein the depth difference between the desired depth of the active trench and the desired depth of the termination trench is minimized, which suppresses the avalanche breakdown induced at the bottom corner of the termination trench close to the active area.