Integrated circuit device having defined gate spacing and method of designing and fabricating thereof

• US 9,431,500 B2
• Filed: 12/12/2013
• Issued: 08/30/2016
• Est. Priority Date: 08/01/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Zhu, Ming, Chen, Po-Nien, Young, Bao-Ru
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US14/104,816
• Publication Number:
  US 20140332893A1
• Time in Patent Office: 992 Days
• Field of Search: 257/499, 257/368, 326 47- 50, 326 41- 42, 326/44, 716110-111, 716118-119, 716/122, 438587-588
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 2223/58 Structural electrical arrangements for semiconductor devices not otherwise provided for
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm²).

Claims

1. An integrated circuit, comprising:

a first gate structure having a first side of a first length (W) and a second side of a second length (L), the first length (W) being greater than the second length (L), wherein W and L are provided in a unit of microns;

a second gate structure spaced a distance in a direction substantially parallel to the second side from the first gate structure, wherein the distance is greater than (√

{square root over (W*W+L*L)})/10, wherein the second gate structure is the next adjacent gate structure to the first gate structure.

2. The device of claim 1, wherein the distance is less than approximately 500 nanometers, and

wherein the first gate structure and the second gate structure are disposed in a single active region.

3. The device of claim 1, further comprising:

a third gate structure spaced a second distance from the first gate structure and disposed on an opposing side of the first gate structure from the second gate structure.

4. The device of claim 3, wherein the third gate structure is smaller than the first gate structure and the second gate structure.

5. The device of claim 3, wherein the second distance is between approximately 100 and approximately 200 nanometers.

6. The device of claim 1, wherein the first gate structure is a metal gate, and wherein the second gate structure is a dummy gate structure including polysilicon.

7. An integrated circuit device, comprising:

a first gate structure having a first side and a second side,

the first side having a first length (W),

the second side having a second length (L),

wherein the first length (W) is greater than the second length (L),

wherein W and L are provided in a unit of microns;

a second gate structure disposed adjacent to the first gate structure; and

a spacing between the first gate structure and the second gate structure in a direction substantially parallel to the second side, the spacing having a distance that is greater than (√

{square root over (W*W+L*L)})/10.

8. The device of claim 7, wherein the distance is less than approximately 500 nanometers, and

wherein the first gate structure has an area of greater than approximately 3 μ

m².

9. The device of claim 7, further comprising:

a third gate structure spaced a second distance from the first gate structure and disposed on an opposing side of the first gate structure from the second gate structure.

10. The device of claim 9, wherein the third gate structure is smaller than the first gate structure and the second gate structure,

wherein the third gate structure has a third side substantially collinear to the second side of the first gate structure, and

wherein the third side has a third length less than the second length.

11. The device of claim 9, wherein the second distance is between approximately 100 and approximately 200 nanometers.

12. The device of claim 7, wherein the first gate structure is a metal gate, and wherein the second gate structure is a dummy gate structure including polysilicon.

13. An integrated circuit, comprising:

a first gate structure having a first side of a first length (W) and a second side of a second length (L), the first length (W) being greater than the second length (L), wherein W and L are provided in a unit of microns; and

a second gate structure spaced a first distance in a direction substantially parallel to the second side from the first gate structure, wherein the first distance is greater than (√

{square root over (W*W+L*L)})/10, wherein the second gate structure is adjacent to the first gate structure; and

a third gate structure spaced a second distance in the direction substantially parallel to the second side from the first gate structure, wherein the third gate structure is smaller than the first gate structure and the second gate structure, and wherein the second distance is less than the first distance.

14. The integrated circuit of claim 13, wherein the first distance is less than approximately 500 nanometers, and wherein the first gate structure has an area of greater than approximately 3 μ

m².

15. The integrated circuit of claim 14, wherein the area of the second gate structure is less than the area of the first gate structure.

16. The integrated circuit of claim 13, wherein the second distance is between approximately 100 and approximately 200 nanometers.

17. The integrated circuit of claim 13, wherein the first gate structure is a metal gate, and wherein the second gate structure is a dummy gate structure including polysilicon.

18. The integrated circuit of claim 13, wherein the second gate structure has a third side substantially collinear to the second side of the first gate structure, and

wherein the third side has a third length substantially similar to the second length.

19. The integrated circuit of claim 13, wherein the third gate structure has a fourth side substantially collinear to the second side of the first gate structure, and

wherein the fourth side has a fourth length less than the second length.

20. The integrated circuit of claim 19, wherein the third gate structure has a fifth side parallel to the first side of the first gate structure, and

wherein the fifth side has a fifth length substantially similar to the first length.