Integrating transistors with different poly-silicon heights on the same die

• US 9,431,503 B2
• Filed: 01/07/2014
• Issued: 08/30/2016
• Est. Priority Date: 03/24/2011
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lin, Chuan, Shiraiwa, Hidehiko, Davis, Bradley Marc, Xue, Lei, Chan, Simon S., Ohtsuka, Kenichi, Hui, Angela T., Bell, Scott Allan
• Primary Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US14/149,521
• Publication Number:
  US 20140117435A1
• Time in Patent Office: 966 Days
• Field of Search: 257/327, 257/392
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28044 the conductor comprising at least another non-silicon conductive layer
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

Claims

1. An integrated circuit, comprising:

at least one first poly-silicon gate region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a plurality of first poly-silicon fingers associated with the first poly-silicon layer, and at least one second poly-silicon finger associated with the second poly-silicon layer, wherein the plurality of first poly-silicon fingers and the at least one second poly-silicon finger are orientated in a substantially orthogonal manner relative to each other; and

wherein a gap between adjacent ones of the first poly-silicon fingers is filled with silicon oxide having a same thickness as a thickness of the first poly-silicon fingers; and

at least one second poly-silicon gate region including the first poly-silicon layer, wherein the at least one first poly-silicon gate region and the at least one second poly-silicon gate region each have different poly-silicon gate structures.

2. The integrated circuit of claim 1, wherein the at least one first poly-silicon gate region includes the first poly-silicon layer and the second poly-silicon layer arranged in a stacked configuration.

3. The integrated circuit of claim 1, wherein the at least one first poly-silicon gate region includes at least one high-voltage transistor and at least one Flash memory transistor.

4. The integrated circuit of claim 1, wherein the at least one second polysilicon gate region includes at least one complex logic device, wherein the at least one complex logic device includes at least one low-voltage transistor.

5. The integrated circuit of claim 4, wherein the at least one complex logic device comprises a microprocessor.

6. The integrated circuit of claim 4, wherein the at least one low-voltage transistor comprises a short-channel transistor device.

7. The integrated circuit of claim 1, wherein the at least one second poly-silicon gate region further includes an oxide layer over the first poly-silicon layer.

8. The integrated circuit of claim 1, wherein the first and the second polysilicon layer each have a thickness of about 500-1000 angstroms.

9. The integrated circuit of claim 1, wherein the at least one first poly-silicon gate region includes at least one Flash memory cell, wherein the at least one Flash memory cell includes at least one Flash memory transistor.

10. The integrated circuit of claim 1, further comprising an oxide between the at least one first poly-silicon finger and another adjacent poly-silicon finger.